MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 523
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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26.3.2.12 Port QS Pin Assignment Register (PQSPAR)
The PQSPAR controls the pin function of port QS.
Freescale Semiconductor
Bits
5–0
7
6
Address
Address
Reset
Reset
R/W:
R/W:
Field
Field
Bits
7
6
PEHPA
PELPA
Name
—
PEHPA
—
R
7
7
Figure 26-25. Port EH/EL Pin Assignment Register (PEHLPAR)
Port EH pin assignment. This bit configures the port EH pins for its primary functions (ETXCLK,
ETXEN, ETXD[0], ECOL, ERXCLK, ERXDV, ERXD[0], ECRS) or digital I/O.
0 Port EH pins configured for digital I/O
1 Port EH pins configured for primary functions (ETXCLK, ETXEN, ETXD[0], ECOL, ERXCLK,
Note: This bit is reserved for the MCF5214 and MCF5216.
Port EL pin assignment. This bit configures the port EL pins for their primary functions (ETXD[3],
ETXD[2], ETXD[1], ETXER, ERXD[3], ERXD[2], ERXD[1], ERXER) or digital I/O.
0 Port EL pins configured for digital I/O
1 Port EL pins configured for primary functions (ETXD[3], ETXD[2], ETXD[1], ETXER, ERXD[3],
Note: Setting 1 is reserved for the MCF5214 and MCF5216.
Reserved, should be cleared.
R/W
Figure 26-26. Port QS Pin Assignment Register (PQSPAR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
ERXDV, ERXD[0], ECRS)
ERXD[2], ERXD[1], ERXER)
PQSPA6
PQSPA6
Name
PELPA
—
6
6
Table 26-15. PEHLPAR Field Descriptions
Table 26-16. PQSPAR Field Description
PQSPA5
Reserved, should be cleared.
Port QS pin assignment 6. This bit configures the port QS6 pin for its
primary function (QSPI_CS3) or digital I/O.
1 Port QS6 pin configured for primary function (QSPI_CS3)
0 Port QS6 pin configured for digital I/O
5
5
IPSBAR + 0x10_0058
IPSBAR + 0x10_0059
PQSPA4
4
0000_0000
0000_0000
Description
PQSPA3
R/W
3
Description
—
R
PQSPA2
2
PQSPA1
1
General Purpose I/O Module
PQSPA0
0
0
26-23
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