MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 537
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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During reset, certain module configurations depend on whether emulation mode is active as determined
by the state of the internal emulation signal.
27.6.3
During reset configuration, the CS0 chip select pin is optionally configured to select an external boot
device. In this case, the V (valid) bit in the CSMR0 register is ignored, and CS0 is enabled after reset. CS0
is asserted for the initial boot fetch accessed from address 0x0000_0000 for the Stack Pointer and address
0x0000_0004 for the program counter (PC). It is assumed that the reset vector loaded from address
0x0000_0004 causes the CPU to start executing from external memory space decoded by CS0.
27.6.4
Output pad strength is determined during reset configuration as shown in
the output pad strength configuration can be changed by programming the LOAD bit of the chip
configuration register.
27.6.5
The clock mode is selected during reset by the CLKMOD pins and reflected in the PLLMODE, PLLSEL,
and PLLREF bits of SYNSR. After reset is exited, the clock mode cannot be changed.
Table 27-11
Freescale Semiconductor
Boot Device Selection
Output Pad Strength Configuration
Clock Mode Selection
summarizes clock mode selection during reset configuration.
1
1
Output pads configured for partial strength
Output pads configured for full strength
When Flash security is enabled, the chip will boot in single chip mode
regardless of the external reset configuration.
Modifying the default configurations is possible only if the external RCON pin is asserted low.
Modifying the default configurations is possible only if the external RCON pin is asserted low.
Chip Configuration
Single-chip mode
Master mode
Reserved
Reserved
Mode
Optional Pin Function Selection
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 27-10. Output Pad Driver Strength Selection
Table 27-9. Chip Configuration Mode Selection
D26 driven high
D26 driven high
D26 driven high
D26 driven low
MODE2
NOTE
CCR Register MODE Field
D17 driven high
D17 driven high
D17 driven low
D17 don’t care
MODE1
CCR Register LOAD Bit
D21 driven high
D21 driven low
Table
1
D16 driven high
D16 driven high
D16 driven low
D16 don’t care
1
Chip Configuration Module (CCM)
27-10. Once reset is exited,
MODE0
27-9
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