MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 21
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.2 Memory Map/Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
24.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.4 Initialization/Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-1
25.2 The CAN System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
25.3 Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
Freescale Semiconductor
23.5.2 UART Module Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23-29
24.1.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-1
24.1.2 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.1.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-2
24.2.1 I
24.2.2 I
24.2.3 I
24.2.4 I
24.2.5 I
24.3.1 START Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-7
24.3.2 Slave Address Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.3.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-8
24.3.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.5 STOP Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.6 Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-9
24.3.7 Clock Synchronization and Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-11
24.3.8 Handshaking and Clock Stretching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.1 Initialization Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.2 Generation of START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-12
24.4.3 Post-Transfer Software Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.4.4 Generation of STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-13
24.4.5 Generation of Repeated START . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
24.4.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
24.4.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-14
25.1.1 FlexCAN Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-2
25.1.2 External Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-3
25.3.1 Message Buffer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25-4
23.5.1.1 Setting up the UART to Generate Core Interrupts . . . . . . . . . . . . . 23-26
23.5.1.2 Setting up the UART to Request DMA Service . . . . . . . . . . . . . . . 23-27
25.3.1.1 Common Fields for Extended and Standard Format Frames . . . . . . 25-5
25.3.1.2 Fields for Extended Format Frames . . . . . . . . . . . . . . . . . . . . . . . . . 25-7
2
2
2
2
2
C Address Register (I2ADR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
C Frequency Divider Register (I2FDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-3
C Control Register (I2CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-4
C Status Register (I2SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-5
C Data I/O Register (I2DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24-6
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
I
2
Chapter 24
Chapter 25
C Interface
FlexCAN
xxi
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