MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 558

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Queued Analog-to-Digital Converter (QADC)
28-20
15, 13
14, 12
11–10
Bit(s)
Address
Reset
R/W:
Field
QS7
Name
TORn
7
CFn
PFn
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
QS6
Figure 28-11. QADC Status Register 0 (QASR0)
6
Queue completion flag. Indicates that a queue scan has been completed. CF[1:2] is
set by the QADC when the input channel sample requested by the last CCW in the
queue is converted, and the result is stored in the result table.
When CFn is set and queue completion interrupts are enabled (QACRn[CIEn] = 1),
the QADC requests an interrupt. The interrupt request is cleared when a 0 is written
to the CF1 bit after it has been read as a 1. Once set, CF1 can be cleared only by a
reset or by writing a 0 to it.
CF[1:2] is updated by the QADC regardless of whether the corresponding interrupt is
enabled. This allows polled recognition of the queue scan completion.
Queue pause flag. Indicates that a queue scan has reached a pause. PF[1:2] is set by
the QADC when the current queue 1 CCW has the pause bit set, the selected input
channel has been converted, and the result has been stored in the result table.
When PFn is set and interrupts are enabled (QACRn[PIEn] = 1), the QADC requests
an interrupt. The interrupt request is cleared when a 0 is written to PFn, after it has
been read as a 1. Once set, PFn can be cleared only by reset or by writing a 0 to it.
PF1:
1 Queue 1 has reached a pause or gate closed before end-of-queue in gated mode.
0 Queue 1 has not reached a pause or gate has not closed before end-of-queue in
PF2:
1 Queue 2 has reached a pause.
0 Queue 2 has not reached a pause.
See
Queue trigger overrun flag. Indicates that an unexpected trigger event has occurred
for queue 1. TOR[1:2] can be set only while the queue is in the active state.
Once set, TOR[1:2] is cleared only by a reset or by writing a 0 to it.
1 At least one unexpected queue 1 trigger event has occurred or queue 1 reaches an
0 No unexpected queue 1 trigger events have occurred.
gated mode.
end-of-queue condition for the second time in externally gated continuous scan.
Table 28-10. QASR0 Field Descriptions
Table 28-11
CWP5
5
IPSBAR + 0x19_0010, 0x19_0011
for a summary of CCW pause bit response in all scan modes.
CWP4
4
0000_0000
R
CWP3
Description
3
CWP2
2
CWP1
1
Freescale Semiconductor
CWP0
0