MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 413
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 413 of 766
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22.4
The QSPI uses a dedicated 80-byte block of static RAM accessible to the module and CPU to perform
queued operations. The RAM is divided into three segments:
Freescale Semiconductor
QSPI_CS
Address: QAR[ADDR]
BITSE
CONT
DSCK
Field
11–8
7–0
DT
15
14
13
12
•
•
Reset
16 command control bytes (command RAM)
32 transmit data bytes (transmit data RAM)
W CONT BITSE
R
Functional Description
Continuous.
0 Chip selects return to inactive level defined by QWR[CSIV] when a single word transfer is complete.
1 Chip selects return to inactive level defined by QWR[CSIV] only after the transfer of the queue entries (max of 16
Note: To keep the chip selects asserted for transfers beyond 16 words, the QWR[CSIV] bit must be set to control
Bits per transfer enable.
0 Eight bits
1 Number of bits set in QMR[BITS]
Delay after transfer enable.
0 Default reset value.
1 The QSPI provides a variable delay at the end of serial transfer to facilitate interfacing with peripherals that have
Chip select to QSPI_CLK delay enable.
0 Chip select valid to QSPI_CLK transition is one-half QSPI_CLK period.
1 QDLYR[QCD] specifies the delay from QSPI_CS valid to QSPI_CLK.
Peripheral chip selects. Used to select an external device for serial data transfer. More than one chip select may be
active at once, and more than one device can be connected to each chip select. Bits 11-8 map directly to the
corresponding QSPI_CSn pins. If more than four chip selects are needed, then an external demultiplexor can be
used with the QSPI_CSn pins.
0 Enable chip select.
1 Mask chip select.
Note: Not all chip selects may be available on all device packages. See
Reserved, must be cleared.
15
—
words).
a latency requirement. The delay between transfers is determined by QDLYR[DTL].
The command RAM is accessed only using the most significant byte of
QDR and indirect addressing based on QAR[ADDR].
the level that the chip selects return to after the first transfer.
on which chip selects are pinned-out.
—
14
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
DT
—
13
Figure 22-9. Command RAM Registers (QCR0–QCR15)
DSCK
Table 22-9. QCR0–QCR15 Field Descriptions
—
12
—
11
10
—
QSPI_CS
NOTE
—
Description
9
—
8
—
0
7
Chapter 14, “Signal Descriptions,”
—
0
6
Queued Serial Peripheral Interface (QSPI)
—
0
5
—
0
4
Access: CPU write-only
—
0
3
—
2
0
—
0
1
for details
—
0
0
22-9
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