MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 365
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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19.2.2
The 16-bit read/write PMRn contains the timer modulus value loaded into the PIT counter when the count
reaches 0x0000 and the PCSRn[RLD] bit is set.
When the PCSRn[OVW] bit is set, PMRn is transparent, and the value written to PMRn is immediately
loaded into the PIT counter. The prescaler counter is reset (0xFFFF) anytime a new value is loaded into
the PIT counter and also during reset. Reading the PMRn returns the value written in the modulus latch.
Reset initializes PMRn to 0xFFFF.
19.2.3
The 16-bit, read-only PCNTRn contains the counter value. Reading the 16-bit counter with two 8-bit reads
is not guaranteed coherent. Writing to PCNTRn has no effect, and write cycles are terminated normally.
Freescale Semiconductor
IPSBAR
Field
Field
Offset:
15–0
RLD
Reset
PM
EN
1
0
W
R
0x15_0002 (PMR0)
0x16_0002 (PMR1)
0x17_0002 (PMR2)
0x18_0002 (PMR3)
Reload bit. The read/write reload bit enables loading the value of PMRn into PIT counter when the count reaches
0x0000.
0 Counter rolls over to 0xFFFF on count of 0x0000
1 Counter reloaded from PMRn on count of 0x0000
PIT enable bit. Enables PIT operation. When PIT is disabled, counter and prescaler are held in a stopped state. This
bit is read anytime, write anytime.
0 PIT disabled
1 PIT enabled
Timer modulus. The value of this register is loaded into the PIT counter when the count reaches zero and the
PCSRn[RLD] bit is set. However, if PCSRn[OVW] is set, the value written to this field is immediately loaded into the
counter. Reading this field returns the value written.
15
1
PIT Modulus Register (PMRn)
PIT Count Register (PCNTRn)
14
1
13
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 19-3. PCSRn Field Descriptions (continued)
12
1
Figure 19-3. PIT Modulus Register (PMRn)
11
Table 19-4. PMRn Field Descriptions
1
10
1
1
9
Description
Description
1
8
PM
1
7
1
6
Programmable Interrupt Timers (PIT0–PIT3)
1
5
4
1
1
3
Access: Supervisor
1
2
1
1
read/write
19-5
1
0
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