MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 107
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.3.5
As discussed in
providing temporary storage for the last fetched line.
With the cache enabled as defined by CACR[CENB], a cacheable fetch that misses in the tag memory and
the line-fill buffer generates an external fetch. For data misses, the size of the external fetch is always 16
bytes. For instruction misses, the size of the external fetch is determined by the value contained in the 2-bit
CLNF field of the CACR and the miss address.
the miss address, and the size of the external fetch.
Depending on the runtime characteristics of the application and the memory response speed, overall
performance may be increased by programming the CLNF bits to values 00 or 01.
For all cases of a line-sized fetch, the critical longword defined by bits [3:2] of the miss address is accessed
first followed by the remaining three longwords that are accessed by incrementing the longword address
in a modulo-16 fashion as shown below:
After an external fetch has been initiated and the data is loaded into the line-fill buffer, the cache maintains
a special most-recently-used indicator that tracks the contents of the associated line-fill buffer versus its
corresponding cache location. At the time of the miss, the hardware indicator is set, marking the line-fill
buffer as most recently used. If a subsequent access occurs to the cache location defined by bits [
bits [
recently used, so the hardware indicator is cleared. In all cases, the indicator defines whether the contents
of the line-fill buffer or the memory data array are most recently used. At the time of the next cache miss,
the contents of the line-fill buffer are written into the memory array if the entire line is present, and the
line-fill buffer data is most recently used compared to the memory array.
Generally, longword references are used for sequential instruction fetches. If the processor branches to an
odd word address, a word-sized instruction fetch is generated.
Freescale Semiconductor
if miss address[3:2] = 00
if miss address[3:2] = 01
if miss address[3:2] = 10
if miss address[3:2] = 11
9
:4] for split configurations of the fill buffer address), the data in the cache memory array is now most
fetch sequence = 0x0, 0x4, 0x8, 0xC
fetch sequence = 0x4, 0x8, 0xC, 0x0
fetch sequence = 0x8, 0xC, 0x0, 0x4
fetch sequence = 0xC, 0x0, 0x4, 0x8
Cache Miss Fetch Algorithm/Line Fills
Section 4.1.2,
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
CLNF[1:0]
00
01
1X
“Introduction,” the cache hardware includes a 16-byte, line-fill buffer for
Table 4-6. Initial Fetch Offset vs. CLNF Bits
Line
Line
Line
00
Longword Address Bits[3:2]
Table 4-6
Line
Line
Line
01
Longword
shows the relationship between the CLNF bits,
Line
Line
10
Longword
Longword
Line
11
10
:4] (or
Cache
4-9
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