MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 222

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Chip Select Module
Table 12-8
12-8
Reset: Other CSCRs
15–14
13–10
Bits
7–6
9
8
5
4
Reset: CSCR0
Name
BSTR Burst read enable. Specifies whether burst reads are used for memory associated with each CSn.
describes CSCRn fields.
BEM
WS
AA
PS
—
—
Address
Field
R/W
Reserved, should be cleared.
Wait states. The number of wait states inserted before an internal transfer acknowledge is generated
(WS = 0 inserts zero wait states, WS = 0xF inserts 15 wait states). If AA = 0, TA must be asserted by
the external system regardless of the number of wait states generated. In that case, the external
transfer acknowledge ends the cycle. An external TA supercedes the generation of an internal TA.
Reserved, should be cleared.
Auto-acknowledge enable. Determines the assertion of the internal transfer acknowledge for accesses
specified by the chip select address.
0 No internal TA is asserted. Cycle is terminated externally.
1 Internal TA is asserted as specified by WS. Note that if AA = 1 for a corresponding CSn and the
Port size. Specifies the width of the data associated with each chip select. It determines where data is
driven during write cycles and where data is sampled during read cycles. See
16-, and 32-Bit Port
00 32-bit port size. Valid data sampled and driven on D[31:0]
01 8-bit port size. Valid data sampled and driven on D[31:24]
1x 16-bit port size. Valid data sampled and driven on D[31:16]
Byte enable mode. Specifies the byte enable operation. Certain SRAMs have byte enables that must
be asserted during reads as well as writes. BEM can be set in the relevant CSCR to provide the
appropriate mode of byte enable in support of these SRAMs.
0 BS is not asserted for read. BS is asserted for data write only.
1 BS is asserted for read and write accesses.
0 Data exceeding the specified port size is broken into individual, port-sized non-burst reads. For
1 Enables data burst reads larger than the specified port size, including longword reads from 8- and
external system asserts an external TA before the wait-state countdown asserts the internal TA, the
cycle is terminated. Burst cycles increment the address bus between each internal termination.
example, a longword read from an 8-bit port is broken into four 8-bit reads.
16-bit ports, word reads from 8-bit ports, and line reads from 8-, 16-, and 32-bit ports.
15
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
—
—
Figure 12-4. Chip Select Control Registers (CSCRn)
14
13
0x08A (CSCR0); 0x096 (CSCR1); 0x0A2 (CSCR2); 0x0AE (CSCR3);
Table 12-8. CSCRn Field Descriptions
Sizing”.
11_11
WS
0x0BA (CSCR4); 0x0C6 (CSCR5); 0x0D2 (CSCR6)
10
—
—
9
Description
Uninitialized
AA PS1 PS0 BEM BSTR BSTW
1
8
R/W
D19 D18
7
6
—
5
4
Section 12.3.1.1, “8-,
Freescale Semiconductor
3
—
2
—
0