MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 544

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Queued Analog-to-Digital Converter (QADC)
28.4.6
V
reference inputs from the power supply signals allows for additional external filtering, which increases
reference voltage precision and stability, and subsequently contributes to a higher degree of conversion
accuracy.
28.4.7
The V
power is required to isolate the sensitive analog circuitry from the normal levels of noise present on the
digital power supply.
28.4.8
V
signals to tolerate 5 volts when configured as inputs and drive 5 volts when configured as outputs.
28.5
The QADC occupies 1 Kbyte, or 512 half-word (16-bit) entries, of address space. Ten half-word registers
are control, port, and status registers, 64 half-word entries are the CCW table, and 64 half-word entries are
the result table which occupies 192 half-word address locations because the result data is readable in three
data alignment formats.
28-6
RH
DDH
and V
DDA
provides 5-V power to the digital I/O functions of QADC port QA and port QB. This allows those
0x19_0000
0x19_0002
0x19_0004
0x19_0006
0x19_0008
0x19_000a
0x19_000c
0x19_000e
0x19_0010
0x19_0012
IPSBAR +
Memory Map
Offset
Voltage Reference Signals
Dedicated Analog Supply Signals
Dedicated Digital I/O Port Supply Signal
and V
RL
V
more
Considerations.
are the dedicated input signals for the high and low reference voltages. Separating the
RH
SSA
and V
signals supply power to the analog subsystems of the QADC module. Dedicated
information,
Table 28-2
Port QA Data Register (PORTQA)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Port QA Data Direction Register
RL
must be set to V
QADC Module Configuration Register (QADCMCR)
(DDRQA)
is the QADC memory map.
MSB
Table 28-2. QADC Memory Map
refer
QADC Test Register (QADCTEST)
QADC Control Register 0 (QACR0)
QADC Control Register 1 (QACR1)
QADC Control Register 2 (QACR2)
QADC Status Register 0 (QASR0)
QADC Status Register 1 (QASR1)
to
DDA
NOTE
Reserved
Section 28.9,
and V
Port QB Data Register (PORTQB)
SSA
Port QB Data Direction Register
3
potential, respectively. For
“Signal
(DDRQB)
2
LSB
Connection
Freescale Semiconductor
Access
S/U
S/U
S/U
S/U
S/U
S/U
S/U
—
S
S
1