MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 329
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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17.4.13 Physical Address Upper Register (PAUR)
PAUR contains the upper 16 bits (bytes 4 and 5) of the 48-bit address used in the address recognition
process to compare with the DA (destination address) field of receive frames with an individual DA. In
addition, this register is used in bytes 4 and 5 of the 6-byte Source Address field when transmitting PAUSE
frames. Bits 15:0 of PAUR contain a constant type field (0x8808) for transmission of PAUSE frames. The
upper 16 bits of this register are not reset and you must initialize it.
17.4.14 Opcode/Pause Duration Register (OPD)
The OPD is read/write accessible. This register contains the 16-bit opcode and 16-bit pause duration fields
used in transmission of a PAUSE frame. The opcode field is a constant value, 0x0001. When another node
detects a PAUSE frame, that node pauses transmission for the duration specified in the pause duration
field. The lower 16 bits of this register are not reset and you must initialize them.
Freescale Semiconductor
PADDR1
PADDR2
31–16
TYPE
Field
Field
31–0
15–0
IPSBAR
IPSBAR
Offset:
Offset:
Reset — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — —
Reset — — — — — — — — — — — — — — — — 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0
Bytes 0 (bits 31:24), 1 (bits 23:16), 2 (bits 15:8), and 3 (bits 7:0) of the 6-byte individual address are used for exact
match and the source address field in PAUSE frames.
Bytes 4 (bits 31:24) and 5 (bits 23:16) of the 6-byte individual address used for exact match, and the source address
field in PAUSE frames.
Type field in PAUSE frames. These 16 read-only bits are a constant value of 0x8808.
W
W
R
R
0x10E4
0x10E8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 17-12. Physical Address Lower Register (PALR)
Figure 17-13. Physical Address Upper Register (PAUR)
PADDR2
Table 17-16. PALR Field Descriptions
Table 17-17. PAUR Field Descriptions
Description
Description
PADDR1
TYPE
8
8
7
7
Access: User read/write
Access: User read/write
Fast Ethernet Controller (FEC)
6
6
5
5
4
4
3
3
2
2
1
1
0
0
17-19
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