MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 362
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Programmable Interrupt Timers (PIT0–PIT3)
In wait mode, the PIT module continues to operate as in run mode and can be configured to exit the
low-power mode by generating an interrupt request. In doze mode with the PCSRn[DOZE] bit set, PIT
module operation stops. In doze mode with the PCSRn[DOZE] bit cleared, doze mode does not affect PIT
operation. When doze mode is exited, PIT continues operating in the state it was in prior to doze mode. In
stop mode, the internal bus clock is absent and PIT module operation stops.
In debug mode with the PCSRn[DBG] bit set, PIT module operation stops. In debug mode with the
PCSRn[DBG] bit cleared, debug mode does not affect PIT operation. When debug mode is exited, the PIT
continues to operate in its pre-debug mode state, but any updates made in debug mode remain.
19.2
This section contains a memory map (see
19-2
IPSBAR Offset
0x15_0000
0x16_0000
0x17_0000
0x18_0000
0x15_0002
0x16_0002
0x17_0002
0x18_0002
PIT 0
PIT 1
PIT 2
PIT 3
Low-power Mode
Memory Map/Register Definition
Debug
Doze
The low-power interrupt control register (LPICR) in the system control
module specifies the interrupt level at or above which the device can be
brought out of a low-power mode.
Wait
Stop
PIT Control and Status Register (PCSRn)
PIT Modulus Register (PMRn)
Table 19-2. Programmable Interrupt Timer Modules Memory Map
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 19-1. PIT Module Operation in Low-power Modes
Normal if PCSRn[DOZE] cleared,
Normal if PCSRn[DBG] cleared,
Register
stopped otherwise
stopped otherwise
Supervisor Access Only Registers
PIT Operation
Stopped
Normal
Table
19-2) and describes the register structure for PIT0–PIT3.
NOTE
N/A
Any interrupt at or above level in LPICR, exit doze
No
No. Any interrupt is serviced upon normal exit
mode if PCSRn[DOZE] is set. Otherwise
interrupt assertion has no effect.
from debug mode
Width
(bits)
16
16
2
Access
R/W
R/W
Mode Exit
1
Reset Value
0xFFFF
0x0000
Freescale Semiconductor
Section/Page
19.2.1/19-3
19.2.2/19-5
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