MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 638
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Debug Support
Unassigned command opcodes are reserved by Freescale. All unused command formats within any
revision level perform a
30.5.3.1 ColdFire BDM Command Format
All ColdFire Family BDM commands include a 16-bit operation word followed by an optional set of one
or more extension words, as shown in
30-20
1
2
Read A/D
register
Write A/D
register
Read
memory
location
Write
memory
location
Dump
memory
block
Fill memory
block
Resume
execution
No operation
Read control
register
Write control
register
Read debug
module
register
Write debug
module
register
Command
General command effect and/or requirements on CPU operation:
- Halted. The CPU must be halted to perform this command.
- Steal. Command generates bus cycles that can be interleaved with bus accesses.
- Parallel. Command is executed in parallel with CPU activity.
0x4 is a three-bit field.
Mnemonic
RAREG
RDREG
WAREG
WDREG
READ
WRITE
DUMP
FILL
GO
NOP
RCREG
WCREG
RDMREG
WDMREG
/
/
Read the selected address or data register and
return the results through the serial interface.
Write the data operand to the specified address or
data register.
Read the data at the memory location specified by
the longword address.
Write the operand data to the memory location
specified by the longword address.
Used with
initial
of the block and to retrieve the first result. A
command retrieves subsequent operands.
Used with
initial
address of the block and to supply the first operand.
A
The pipeline is flushed and refilled before resuming
instruction execution at the current PC.
Perform no operation; may be used as a null
command.
Read the system control register.
Write the operand data to the system control
register.
Read the debug module register.
Write the operand data to the debug module
register.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOP
FILL
READ
WRITE
and return the illegal command response.
command writes subsequent operands.
READ
WRITE
is executed to set up the starting address
Table 30-17. BDM Command Summary
is executed to set up the starting
to dump large blocks of memory. An
to fill large blocks of memory. An
Figure
Description
30-15.
DUMP
Parallel
Parallel
Parallel
State
Halted
Halted
Halted
Halted
Halted
Steal
Steal
Steal
Steal
CPU
1
30.5.3.3.10 0x2880
30.5.3.3.11 0x2D {0x4
30.5.3.3.12 0x2C {0x4
30.5.3.3.1 0x218 {A/D,
30.5.3.3.2 0x208 {A/D,
30.5.3.3.3 0x1900—byte
30.5.3.3.4 0x1800—byte
30.5.3.3.5 0x1D00—byte
30.5.3.3.6 0x1C00—byte
30.5.3.3.7 0x0C00
30.5.3.3.8 0x0000
30.5.3.3.9 0x2980
Section
Freescale Semiconductor
Reg[2:0]}
Reg[2:0]}
0x1940—word
0x1980—longword
0x1840—word
0x1880—longword
0x1D40—word
0x1D80—longword
0x1C40—word
0x1C80—longword
DRc[4:0]}
DRc[4:0]}
Command
(Hex)
2
2
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