MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 129
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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initiated by the CPU. Special cases of user mode apply when the CPU is in low-power or debug modes
and when the MCU boots in master mode or emulation mode.
6.4.1
A valid read operation occurs whenever a transfer request is initiated by the ColdFire core, the address is
equal to an address within the valid range of the CFM memory space, and the read/write control indicates
a read cycle.
In order to reduce power at low system clock frequencies, the sense amplifier timeout (SATO) block
minimizes the time during which the sense amplifiers are enabled for read operations. The sense amplifier
enable signals to the Flash timeout after approximately 50 ns.
6.4.2
A valid write operation occurs whenever a transfer request is initiated by the ColdFire core, the address is
equal to an address within the valid range of the CFM memory space, and the read/write control indicates
a write cycle.
The action taken on a valid CFM array write depends on the subsequent user command issued as part of a
valid command sequence. Only aligned 32-bit write operations are allowed to the CFM array. Byte and
word write operations will result in a cycle termination transfer error.
6.4.3
Read and write operations are both used for the program and erase algorithms described in this subsection.
These algorithms are controlled by a state machine whose timebase is derived from the CFM module clock
via a programmable counter.
The command register and associated address and data buffers operate as a two stage FIFO so that a new
command along with the necessary address and data can be stored while the previous command is still in
progress. This pipelining speeds when programming more than one longword on a specific row, as the
charge pumps can be kept on in between two programming commands, thus saving the overhead needed
to set up the charge pumps. Buffer empty and command completion are indicated by flags in the CFM user
status register. Interrupts will be requested if enabled.
6.4.3.1
Prior to issuing any program or erase commands, CFMCLKD must be written to set the Flash state
machine clock (FCLK). The CFM module runs at the system clock frequency ÷ 2, but FCLK must be
divided down from this frequency to a frequency between 150 kHz and 200 kHz. Use the following
procedure to set the PRDIV8 and DIV[5:0] bits in CFMCLKD:
Freescale Semiconductor
1. If f
2. Determine DIV[5:0] by using the following equation. Keep only the integer portion of the result
3. Thus the Flash state machine clock will be:
and discard any fraction. Do not round the result.
SYS
Read Operations
Write Operations
Program and Erase Operations
Setting the CFMCLKD Register
÷ 2 is greater than 12.8 MHz, PRDIV8 = 1; otherwise PRDIV8 = 0.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
DIV[5:0] =
2 x 200kHz x (1 + (PRDIV8 x 7))
f
SYS
ColdFire Flash Module (CFM)
6-17
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