MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 448

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

UART Modules
To configure the UART for DMA requests:
Table 23-14
23-28
1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA
2. Disable interrupts using the UIMR register. The appropriate UIMR bits must be cleared so that
3. Enable DMA access to the UARTn registers by setting the corresponding PACR register in the
4. Enable DMA access to SRAM by setting the SPV bit in the core RAMBAR, and the BDE bit in
5. Initialize the DMA channel. The DMA should be configured for cycle steal mode and a source and
6. For a transmit process:
7. For a receive process:
8. Start the data transfer by setting DCRn[EEXT], which enables the UART channel to issue DMA
channels. For example, setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to
DMA channel 1, setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA
channel 2, and so on. It is possible to independently map transmit-based and receive-based UART
DMA requests in the DMAREQC.
interrupt requests are disabled for those conditions for which a DMA request is desired. For
example, to generate transmit DMA requests from UART1, UIMR1[TXRDY] should be cleared.
This prevents TXRDY from generating an interrupt request while a transmit DMA request is
generated.
SCM for read/write in supervisor and user modes.
the SCM RAMBAR
destination size of one byte. This causes a single byte to be transferred for each UART DMA
request. Set the disable request bit (DCRn[D_REQ] to disable external requests when the BCR
reaches zero.
— Set the DMA SAR register to the address of the source data
— Set DCRn[SINC] to increment the source pointer
— Set DAR to the address if the UART transmit buffer (UTB)
— Clear DCRn[DINC]
— Set BCR to the number of bytes to transmit.
— Set the DMA SAR register to the address of the UART receive buffer (URB)
— Clear DCRn[SINC]
— Set DAR to the address of the source data
— Set DCRn[DINC] to increment the destination pointer
— Set BCR to the number of bytes to transmit.
requests.
shows the DMA requests.
Register
UISRn
UISRn
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Bit
1
0
Table 23-14. UART DMA Requests
Receive DMA request
Transmit DMA request
DMA Request
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