MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 584
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Queued Analog-to-Digital Converter (QADC)
Boundary conditions also exist for combinations of pause and end-of-queue. One case is when a pause bit
is in one CCW and an end-of-queue condition is in the next CCW. The conversion specified by the CCW
with the pause bit set completes normally. The pause flag is set. However, because the end-of-queue
condition is recognized, the completion flag is also set and the queue status becomes idle, not paused.
Examples of this situation include:
Another pause and end-of-queue boundary condition occurs when the pause and an end-of-queue
condition occur in the same CCW. Both the pause and end-of-queue conditions are recognized
simultaneously. The end-of-queue condition has precedence so a conversion is not performed for the CCW
and the pause flag is not set. The QADC sets the completion flag and the queue status becomes idle.
Examples of this situation are:
28.8.3
The QADC queuing mechanism allows application software to utilize different requirements for
automatically scanning input channels.
In single-scan mode, a single pass through a sequence of conversions defined by a queue is performed. In
continuous-scan mode, multiple passes through a sequence of conversions defined by a queue are
executed.
The possible modes are:
The following paragraphs describe single-scan and continuous-scan operations.
28-46
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BQ2 (beginning of queue 2) is set beyond the end of the CCW table (64–127) and a trigger event
occurs on queue 2. The end-of-queue condition is recognized immediately, the completion flag is
set, and the queue becomes idle. A conversion is not performed.
The pause bit is set in CCW5 and the channel 63 (EOQ) code is in CCW6.
The pause is in CCW63.
During queue 1 operation, the pause bit is set in CCW20 and BQ2 points to CCW21.
The pause bit is set in CCW10 and EOQ is programmed into CCW10.
During queue 1 operation, the pause bit set in CCW32, which is also BQ2.
Disabled mode and reserved mode
Software-initiated single-scan mode
Externally triggered single-scan mode
Externally gated single-scan mode
Interval timer single-scan mode
Software-initiated continuous-scan mode
Externally triggered continuous-scan mode
Externally gated continuous-scan mode
Periodic timer continuous-scan mode
Scan Modes
Multiple end-of-queue conditions may be recognized simultaneously,
although there is no change in QADC behavior. For example, if BQ2 is set
to CCW0, CCW0 contains the EOQ code, and a trigger event occurs on
queue 1, the QADC reads CCW0 and detects both end-of-queue conditions.
The completion flag is set and queue 1 becomes idle.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE
Freescale Semiconductor
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