MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 460
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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I
24.2.5
In master-receive mode, reading I2DR allows a read to occur and for the next data byte to be received. In
slave mode, the same function is available after the I
24-6
2
C Interface
RXAK
Field
IAAS
SRW
ICF
IBB
IAL
IIF
7
6
5
4
3
2
1
0
I
0 Transfer in progress
1 Transfer complete. Set by falling edge of ninth clock of a byte transfer.
I
its TX/RX mode accordingly. Writing to I2CR clears this bit.
0 Not addressed.
1 Addressed as a slave. Set when its own address (IADR) matches the calling address.
I
0 Bus is idle. If a STOP signal is detected, IBB is cleared.
1 Bus is busy. When START is detected, IBB is set.
I
to it.)
Reserved, must be cleared.
Slave read/write. When IAAS is set, SRW indicates the value of the R/W command bit of the calling address sent
from the master. SRW is valid only when a complete transfer has occurred, no other transfers have been initiated,
and the I
0 Slave receive, master writing to slave.
1 Slave transmit, master reading from slave.
I
0 No I
1 An interrupt is pending, which causes a processor interrupt request (if IIEN = 1). Set when one of the following
Received acknowledge. The value of I2C_SDA during the acknowledge bit of a bus cycle.
0 An acknowledge signal was received after the completion of 8-bit data transmission on the bus
1 No acknowledge signal was detected at the ninth clock.
2
2
2
2
• I2C_SDA sampled low when the master drives high during an address or data-transmit cycle.
• I2C_SDA sampled low when the master drives high during the acknowledge bit of a data-receive cycle.
• A start cycle is attempted when the bus is busy.
• A repeated start cycle is requested in slave mode.
• A stop condition is detected when the master did not request it.
2
• Complete one byte transfer (set at the falling edge of the ninth clock)
• Reception of a calling address that matches its own specific address in slave-receive mode
• Arbitration lost
C Data transferring bit. While one byte of data is transferred, ICF is cleared.
C addressed as a slave bit. The CPU is interrupted if I2CR[IIEN] is set. Next, the CPU must check SRW and set
C bus busy bit. Indicates the status of the bus.
C arbitration lost. Set by hardware in the following circumstances. (IAL must be cleared by software by writing zero
C interrupt. Must be cleared by software by writing a 0 in the interrupt routine.
occurs:
I
2
C Data I/O Register (I2DR)
2
C interrupt pending
2
C module is a slave and has an address match.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 24-5. I2SR Field Descriptions
Description
2
C has received its slave address.
Freescale Semiconductor
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