MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 739
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
Table 17-29 on page
Table 17-30 on page
Table 23-10 on page
Figure 12-4 on page
Figure 18-1 on page
Chapter 8, “System
Table 14-1 on page
Table 19-3 on page
Figure 8-2 on page
Figure 9-2 on page
Table 8-5 on page
Table 9-7 on page
Chapter 12, “Chip
Figure 23-12 on
Control Module
Select Module
17.4.21/17-23
19.3.3/19-7
page 23-14
(SCM)
8.5.2.1/8-9
Location
16.2/16-2
17-28
17-29
23-14
9-10
12-8
14-3
18-2
19-4
8-4
8-6
9-4
and
Moved information in Section 8.4.6, “DMA Request Control Register,” to
Control
Changed offset for the copy of RAMBAR to “0x008.”
Changed CWTIC to CWTIF.
Changed text to read “Setting MPARK[PRK_LAST] causes the arbitration pointer to be parked on the
highest priority master.”
Changed “÷ MFD (2–9)” to “÷ MFD (4–18).”
Changed equation in “Normal PLL Clock Mode” row to the following:
f
Eliminated Section 12.4.1.4, “Code Example.”
In “Reset: CSCR0” row, changed “D7, D6, D5” to “—, D19, D18.”
Replaced “SCKE” with “SCKE.”
Changed text to read “The transmit FIFO uses addresses from the start of the FIFO to the location four
bytes before the address programmed into the FRSR.”
Added the following footnote: “The receive buffer pointer, which contains the address of the associated
data buffer, must always be evenly divisible by 16. The buffer must reside in memory external to the FEC.
This value is never modified by the Ethernet controller.”
Added the following footnote: “The transmit buffer pointer, which contains the address of the associated
data buffer, must always be evenly divisible by 4. The buffer must reside in memory external to the FEC.
This value is never modified by the Ethernet controller.”
Changed value in “Divide by” block to 8192.
Multiplied all system clock divisor values in PRE field description by 2.
Changed equation in text to the following:
Timeout period = PRE[3:0] × (PM[15:0] + 1) × system clock ÷ 2
In “UISR Field” row, changed bit 6 to a reserved bit.
Changed bit 6 to a reserved bit.
sys
= f
ref
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
(DMAREQC).”
× 2(MFD + 2)/2
Table B-2. Rev. 0.1 to Rev. 1 Changes (continued)
RFD
Description
Section 16.2, “DMA Request
Revision History
B-3
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