MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 488
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 488 of 766
- Download datasheet (9Mb)
FlexCAN
25.5.1
Table 25-8
25-18
Bits
15
14
13
12
11
10
Address
Reset
Reset
Field
Field
R/W
R/W
WAKEMS
CAN Module Configuration Register (CANMCR)
describes the CANMCR fields.
NOTRDY
Name
STOP
HALT
FRZ
—
K
SUPV
STOP
15
7
by the CPU or by the FlexCAN, if the SELFWAKE bit is set.
0 Enable FlexCAN clocks
1 Disable FlexCAN clocks
FREEZE assertion response. When FRZ = 1, the FlexCAN can enter debug mode when the BKPT
line is asserted or the HALT bit is set. Clearing this bit field causes the FlexCAN to exit debug
mode. Refer to
0 FlexCAN ignores the BKPT signal and the HALT bit in the module configuration register.
1 FlexCAN module enabled to enter debug mode.
Reserved
Halt FlexCAN S-Clock. Setting the HALT bit has the same effect as assertion of the BKPT signal
on the FlexCAN without requiring that BKPT be asserted. This bit is set to one after reset. It should
be cleared after initializing the message buffers and control registers. FlexCAN message buffer
receive and transmit functions are inactive until this bit is cleared.
When HALT is set, write access to certain registers and bits that are normally read-only is allowed.
0 The FlexCAN operates normally
1 FlexCAN enters debug mode if FRZ = 1
FlexCAN not ready. This bit indicates that the FlexCAN is either in low-power stop mode or debug
mode. This bit is read-only and is set only when the FlexCAN enters low-power stop mode or
debug mode. It is cleared once the FlexCAN exits either mode, either by synchronization to the
CAN bus or by the self-wake mechanism.
0 FlexCAN has exited low-power stop mode or debug mode.
1 FlexCAN is in low-power stop mode or debug mode.
Wakeup interrupt mask. The WAKEMSK bit enables wake-up interrupt requests.
0 Wake up interrupt is disabled.
1 Wake up interrupt is enabled.
Low-power stop mode enable. The STOP bit may only be set by the CPU. It may be cleared either
Figure 25-6. CAN Module Configuration Register (CANMCR)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
SELFWAKE
FRZ
14
6
Table 25-8. CANMCR Field Descriptions
Section 25.4.11.1, “Debug
APS
—
13
5
STOPACK
IPSBAR + 0x1C_0000
HALT
12
4
0101_1001
1000_0000
Description
R/W
R/W
Mode” for more information.
NOTRDY
11
3
WAKEMSK SOFTRST
10
—
Freescale Semiconductor
9
FRZACK
8
0
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