MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 153
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 153 of 766
- Download datasheet (9Mb)
Chapter 8
System Control Module (SCM)
This section details the functionality of the System Control Module (SCM) which provides the
programming model for the System Access Control Unit (SACU), the system bus arbiter, a 32-bit core
watchdog timer (CWT), and the system control registers and logic. Specifically, the system control
includes the internal peripheral system (IPS) base address register (IPSBAR), the processor’s dual-port
RAM base address register (RAMBAR), and system control registers that include the core watchdog timer
control.
8.1
The SCM provides the control and status for a variety of functions including base addressing and address
space masking for both the IPS peripherals and resources (IPSBAR) and the ColdFire core memory spaces
(RAMBAR). The CPU core supports two memory banks, one for the internal SRAM and the other for the
internal Flash.
The SACU provides the mechanism needed to implement secure bus transactions to the system address
space.
The programming model for the system bus arbitration resides in the SCM. The SCM sources the
necessary control signals to the arbiter for bus master management.
The CWT provides a means of preventing system lockup due to uncontrolled software loops via a special
software service sequence. If periodic software servicing action does not occur, the CWT times out with a
programmed response (interrupt) to allow recovery or corrective action to be taken.
8.2
The SCM includes these distinctive features:
Freescale Semiconductor
•
•
•
•
•
IPS base address register (IPSBAR)
— Base address location for 1-Gbyte peripheral space
— User control bits
Processor-local memory base address register (RAMBAR)
System control registers
— Core reset status register (CRSR) indicates type of last reset
— Core watchdog control register (CWCR) for watchdog timer control
— Core watchdog service register (CWSR) to service watchdog timer
System bus master arbitration programming model (MPARK)
System access control unit (SACU) programming model
— Master privilege register (MPR)
— Peripheral access control registers (PACRs)
— Grouped peripheral access control registers (GPACR0, GPACR1)
Overview
Features
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
8-1
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