MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 230

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

External Interface Module (EIM)
13.4.3
During a read cycle, the device receives data from memory or from a peripheral device.
read cycle flowchart.
The read cycle timing diagram is shown in
13-6
S5
State
Read Cycle
S5
Read
Write
1.
2.
3.
4.
5.
1.
1.
Cycle
An external device has at most two CLKOUT cycles after the start of S4 to
three-state the data bus. This applies to basic read cycles, fast termination
cycles, and the last transfer of a burst.
In the following timing diagrams, TA waveforms apply for chip selects
programmed to enable either internal or external termination. TA assertion
should look the same in either case.
Set R/W to read
Place address on A[31:0]
Assert TIP, and SIZ[1:0]
Assert TS
Negate TS
Sample TA low and latch data
Start next cycle
ColdFire processor
Low
CLKOUT
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 13-3. Bus Cycle States (continued)
CS, BS, and OE are negated on the CLKOUT falling edge of S5. The processor
stops driving address lines and R/W on the rising edge of CLKOUT, terminating the
read or write cycle. At the same time, the processor negates TIP, and SIZ[1:0] on
the rising edge of CLKOUT.
Note that the rising edge of CLKOUT may be the start of S0 for the next access
cycle.
The external device stops driving data between S4 and S5.
The data bus returns to high impedance on the rising edge of CLKOUT. The rising
edge of CLKOUT may be the start of S0 for the next access.
Figure 13-5. Read Cycle Flowchart
Figure
NOTE
NOTE
13-6.
Description
1.
2.
3.
1.
2.
Decode address and select the
appropriate slave device.
Drive data on D[31:0]
Assert TA
Negate TA.
Stop driving D[31:0]
External device
Freescale Semiconductor
Figure 13-5
is a