MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 341
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Other registers reset when the ECR[ETHER_EN] bit is cleared (which is accomplished by a hard reset or
software to halt operation). By clearing ECR[ETHER_EN], configuration control registers such as the
TCR and RCR are not reset, but the entire data path is reset.
17.5.3
You need to initialize portions the FEC prior to setting the ECR[ETHER_EN] bit. The exact values depend
on the particular application. The sequence is not important.
Table 17-32
Table 17-33
Freescale Semiconductor
User Initialization (Prior to Setting ECR[ETHER_EN])
defines Ethernet MAC registers requiring initialization.
defines FEC FIFO/DMA registers that require initialization.
Table 17-33. FEC User Initialization (Before ECR[ETHER_EN])
Descriptor Controller block
Table 17-31. ECR[ETHER_EN] De-Assertion Effect on FEC
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 17-32. User Initialization (Before ECR[ETHER_EN])
Register/Machine
RECV block
XMIT block
DMA block
PALR / PAUR (only needed for full duplex flow control)
RDAR
TDAR
OPD (only needed for full duplex flow control)
Clear EIR (write 0xFFFF_FFFF)
Initialize FRSR (optional)
Initialize EMRBR
TFWR (optional)
MSCR (optional)
Initialize ERDSR
Clear MIB_RAM
Initialize ETDSR
GAUR / GALR
Initialize EIMR
Description
Description
IALR / IAUR
RCR
TCR
Transmission is aborted (bad CRC
All DMA activity is terminated
Receive activity is aborted
Halt operation
Reset Value
appended)
Cleared
Cleared
Fast Ethernet Controller (FEC)
17-31
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