MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 383
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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20.5.16 Pulse Accumulator Flag Register (GPTPAFLG)
Freescale Semiconductor
Bit(s)
Bit(s)
7–2
1
0
1
0
Address
When the fast flag clear all enable bit, GPTSCR1[TFFCA], is set, any access
to the pulse accumulator counter registers clears all the flags in GPTPAFLG.
Reset
Field
R/W
PAOVF
PAOVI
Name
Name
PAIF
PAI
—
Figure 20-18. Pulse Accumulator Flag Register (GPTPAFLG)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 20-18. GPTPACTL Field Descriptions (continued)
7
Pulse accumulator overflow interrupt enable. Enables the PAOVF flag to generate
interrupt requests.
1 PAOVF interrupt requests enabled
0 PAOVF interrupt requests disabled
Pulse accumulator input interrupt enable. Enables the PAIF flag to generate interrupt
requests.
1 PAIF interrupt requests enabled
0 PAIF interrupt requests disabled
Reserved, should be cleared.
Pulse accumulator overflow flag. Set when the 16-bit pulse accumulator rolls over from
0xFFFF to 0x0000. If the GPTPACTL[PAOVI] bit is also set, PAOVF generates an
interrupt request. Clear PAOVF by writing a 1 to it. This bit is read anytime, write
anytime. (Writing 1 clears the flag; writing 0 has no effect.)
1 Pulse accumulator overflow
0 No pulse accumulator overflow
Pulse accumulator input flag. Set when the selected edge is detected at the PAI pin.
In event counter mode, the event edge sets PAIF. In gated time accumulation mode,
the trailing edge of the gate signal at the PAI pin sets PAIF. If the PAI bit in GPTPACTL
is also set, PAIF generates an interrupt request. Clear PAIF by writing a 1 to it.
1 Active PAI input
0 No active PAI input
Table 20-19. GPTPAFLG Field Descriptions
IPSBAR + 0x1A_0019, 0x1B_0019
—
NOTE
0000_0000
R/W
Description
Description
General Purpose Timer Modules (GPTA and GPTB)
2
PAOVF
1
PAIF
0
20-15
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