MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 464
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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I
Various combinations of read/write formats are then possible:
24-10
2
C Interface
I2C_SCL
I2C_SDA
•
•
•
Example 1:
Example 2:
Example 3:
ST
Note: No acknowledge on the last byte
The first example in
The transfer direction is not changed.
The second example in
At the moment of the first acknowledge, the master-transmitter becomes a master-receiver and the
slave-receiver becomes slave-transmitter.
In the third example in
repeated START signal. This is to communicate with same slave in a different mode without
releasing the bus. The master transmits data to the slave first, and then the master reads data from
slave by reversing the R/W bit.
7-bit Slave
Address
START
Signal
ST = Start
SP = Stop
A = Acknowledge (
A = Not Acknowledge (
Rept ST = Repeated Start
ST
ST
msb
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
1
7bit Slave Address
7bit Slave Address
2
Master Reads from Slave
R/W
1
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Calling Address
I2C_
3
A
I2C_
Figure 24-11
SDA low)
4
Figure 24-11. Data Transfer, Combined Format
Figure 24-11
Figure
SDA high)
Data
5
R/W
R/W
6
Figure 24-10. Repeated START
24-11, START condition and slave address are repeated using the
0
1
lsb
7
is the case of master-transmitter transmitting to slave-receiver.
A
A
A
is the master reading the slave immediately after the first byte.
R/W
8
Rept
ST
ACK
Bit
9
Data
Data
XX
7-bit Slave
Address
Repeated
START
Signal
From Master to Slave
From Slave to Master
AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W
msb
A
1
A
A
R/W
0
2
A
New Calling Address
Data
Data
3
Master Writes to Slave
Data
4
A/A
5
A
SP
SP
6
A
Freescale Semiconductor
lsb
Data
7
R/W
8
A/A
ACK
No
9
Bit
SP
STOP
Signal
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