MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 376

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

General Purpose Timer Modules (GPTA and GPTB)
20.5.6
20-8
Bit(s)
Bit(s)
15–0
6–5
3–0
7
4
GPT System Control Register 1 (GPTSCR1)
Address
Reset
Field
R/W
GPTEN
TFFCA
Name
CNTR
Name
—
—
GPTEN
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 20-7. GPT System Control Register 1 (GPTSCR1)
7
Read-only field that provides the current count of the timer counter. To ensure
coherent reading of the timer counter, such that a timer rollover does not occur
between two back-to-back 8-bit reads, it is recommended that only word (16-bit)
accesses be used.
A write to GPTCNT may have an extra cycle on the first count because the write is not
synchronized with the prescaler clock. The write occurs at least one cycle before the
synchronization of the prescaler clock.
These bits are read anytime. They should be written to only in test (special) mode;
writing to them has no effect in normal modes.
Enables the general purpose timer. When the timer is disabled, only the registers are
accessible. Clearing GPTEN reduces power consumption. These bits are read
anytime, write anytime.
1 GPT enabled
0 GPT and GPT counter disabled
Reserved, should be cleared.
Timer fast flag clear all. Enables fast clearing of the main timer interrupt flag registers
(GPTFLG1 and GPTFLG2) and the PA flag register (GPTPAFLG). TFFCA eliminates
the software overhead of a separate clear sequence. See
When TFFCA is set:
Writing logic 1s to the flags clears them only when TFFCA is clear.
1 Fast flag clearing
0 Normal flag clearing
Reserved, should be cleared.
• An input capture read or a write to an output compare channel clears the
• Any access of the GPT count registers (GPTCNTH/L) clears the TOF flag.
• Any access of the PA counter registers (GPTPACNT) clears both the PAOVF and
corresponding channel flag, CxF.
PAIF flags in GPTPAFLG.
Table 20-9. GPTSCR1 Field Descriptions
Table 20-8. GPTCNT Field Descriptions
6
—
IPSBAR + 0x1A_0006, 0x1B_0006
5
TFFCA
0000_0000
4
R/W
Description
3
Description
—
Figure
Freescale Semiconductor
20-8.
0