MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 461

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

24.3
The I
I
The logic AND function is exercised on both lines with external pull-up resistors.
Out of reset, the I
responding to a slave transmit address, the I
Section 24.4.1, “Initialization Sequence,”
Normally, a standard communication is composed of four parts: START signal, slave address transmission,
data transfer, and STOP signal. These are discussed in the following sections.
24.3.1
When no other device is bus master (I2C_SCL and I2C_SDA lines are at logic high), a device can initiate
communication by sending a START signal (see A in
high-to-low transition of I2C_SDA while I2C_SCL is high. This signal denotes the beginning of a data
transfer (each data transfer can be several bytes long) and awakens all slaves.
Freescale Semiconductor
2
C compliance, all devices connected to these two signals must have open drain or open collector outputs.
Field
DATA
7–0
IPSBAR
2
C module uses a serial data line (I2C_SDA) and a serial clock line (I2C_SCL) for data transfer. For
Offset:
Reset:
I
bit is sent first. In master receive mode, reading this register initiates the reception of the next byte of data. In slave
mode, the same functions are available after an address match has occurred.
Note: In master transmit mode, the first byte of data written to I2DR following assertion of I2CR[MSTA] is used for
Note: I2CR[MSTA] generates a start when a master does not already own the bus. I2CR[RSTA] generates a start
Functional Description
W
2
R
C data. When data is written to this register in master transmit mode, a data transfer is initiated. The most significant
START Signal
0x00_0310 (I2DR)
the address transfer and should comprise the calling address (in position D7–D1) concatenated with the
required R/W bit (in position D0). This bit (D0) is not automatically appended by the hardware, software must
provide the appropriate R/W bit.
(restart) without the master first issuing a stop (i.e., the master already owns the bus). To start the read of data,
a dummy read to this register starts the read process from the slave. The next read of the I2DR register
contains the actual data.
2
0
7
C default state is as a slave receiver. Therefore, when not programmed to be a master or
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
6
0
Figure 24-6. I
Table 24-6. I2DR Field Description
0
5
for exceptions.
2
C module should return to the default slave receiver state. See
2
C Data I/O Register (I2DR)
0
4
Description
Figure
DATA
24-7). A START signal is defined as a
0
3
0
2
Access: User read/write
0
1
I
2
0
0
C Interface
24-7