MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 177
MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
14–12
Bit(s)
10–8
11
LOCRE
Name
MFD
RFD
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 9-4. SYNCR Field Descriptions (continued)
Multiplication Factor Divider. Contain the binary value of the divider in the PLL
feedback loop. The MFD[2:0] value is the multiplication factor applied to the reference
frequency. When MFD[2:0] are changed or the PLL is disabled in stop mode, the PLL
loses lock. In 1:1 PLL mode, MFD[2:0] are ignored, and the multiplication factor is one.
Note: In external clock mode, the MFD[2:0] bits have no effect.
Loss-of-clock reset enable. Determines how the system handles a loss-of-clock
condition. When the LOCEN bit is clear, LOCRE has no effect. If the LOCS flag in
SYNSR indicates a loss-of-clock condition, setting the LOCRE bit causes an
immediate reset. To prevent an immediate reset, the LOCRE bit must be cleared
before entering stop mode with the PLL disabled.
1 Reset on loss-of-clock
0 No reset on loss-of-clock
Note: In external clock mode, the LOCRE bit has no effect.
Reduced frequency divider field. The binary value written to RFD[2:0] is the PLL
frequency divisor. See table in MFD bit description. Changing RFD[2:0] does not affect
the PLL or cause a relock delay. Changes in clock frequency are synchronized to the
next falling edge of the current system clock. To avoid surpassing the allowable system
operating frequency, write to RFD[2:0] only when the LOCK bit is set.
The following table illustrates the system frequency multiplier of the reference
frequency
1
2
3
((
where f
device (66 MHz or 80 MHz).
MFD = 000 not valid for f
Default value out of reset
f
sys
111 (÷ 128)
=
100 (÷ 16)
101 (÷ 32)
110 (÷ 64)
001 (÷ 2)
000 (÷ 1)
010 (÷ 4)
011 (÷ 8)
1
f
--------------------------------------------- - f
sys(max)
ref
in normal PLL mode.
×
2 MFD
2
(
3
RFD
is the maximum system frequency for the particular MCF5282
000
1/16
1/32
(4x)
1/2
1/4
1/8
+
4
2
1
2
2
)
ref
;
3/16
3/32
3/64
ref
(6x)
< 3 MHz
001
3/2
3/4
3/8
6
3
×
Description
2 MFD
(
(8x)
1/16
010
1/4
1/8
1/2
8
4
2
1
(3)
+
2
(10x)
5/16
5/32
5/64
011
MFD[2:0]
5/2
5/4
5/8
)
10
5
≤
f
sys max
(12x)
3/16
3/32
100
(
3/2
3/4
3/8
12
6
3
)
;
(14x)
f
7/16
7/32
7/64
101
sys
7/2
7/4
7/8
14
7
≤
f
sys max
(16x)
110
1/2
1/4
1/8
16
8
4
2
1
(
)
(18x)
9/16
9/32
9/64
111
,
9/2
9/4
9/8
18
Clock Module
9
9-7
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