MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 164

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

System Control Module (SCM)
8.6.2
Each bus transfer can be classified by its privilege level and the reference type. The complete set of access
types includes:
Instruction fetch accesses are associated with the execute attribute.
It should be noted that while the bus does not implement the concept of reference type (code versus data)
and only supports the user/supervisor privilege level, the reference type attribute is supported by the
system bus. Accordingly, the access checking associated with both privilege level and reference type is
performed in the IPS controller using the attributes associated with the reference from the system bus.
The SACU partitions the access control mechanisms into three distinct functions:
8.6.3
The memory map for the SACU program-visible registers within the System Control Module (SCM) is
shown in
8-12
•
•
•
•
•
•
•
•
Supervisor instruction fetch
Supervisor operand read
Supervisor operand write
User instruction fetch
User operand read
User operand write
Master privilege register (MPR)
— Allows each bus master to be assigned a privilege level:
— The reset state provides supervisor privilege to the processor core (bus master 0).
— Input signals allow the non-core bus masters to have their user/supervisor attribute enabled at
Peripheral access control registers (PACRs)
— Nine 8-bit registers control access to 17 of the on-chip peripheral modules.
— Provides read/write access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to these modules
— Grouped peripheral access control registers (GPACR0, GPACR1)
— One single register (GPACR0) controls access to 14 of the on-chip peripheral modules
— One register (GPACR1) controls access for IPS reads and writes to the Flash module
— Provide read/write/execute access rights, supervisor/user privilege levels
— Reset state provides supervisor-only read/write access to each of these peripheral spaces
Figure
Features
– Disable the master’s user/supervisor attribute and force to user mode access
– Enable the master’s user/supervisor attribute
reset. This is intended to support the concept of a trusted bus master, and also controls the
ability of a bus master to modify the register state of any of the SACU control registers; that is,
only trusted masters can modify the control registers.
Memory Map/Register Definition
8-7. The MPR, PACR, and GPACRs are 8 bits in width.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Freescale Semiconductor