MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 118
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 118 of 766
- Download datasheet (9Mb)
ColdFire Flash Module (CFM)
6-6
Address
Reset
Reset
Field BA31 BA30 BA29 BA28 BA27 BA26 BA25 BA24 BA23 BA22 BA21 BA20 BA19
Field
R/W
R/W
Note: The reset value for the valid bit is determined by the chip mode selected at reset (see
“Chip Configuration Module
Flash accesses (reads/writes) by a bus master other than the core, (DMA
controller or Fast Ethernet Controller), or writes to Flash by the core during
programming must use the backdoor Flash address of IPSBAR plus an
offset of 0x0400_0000. For example, for a DMA transfer from the first
location of Flash when IPSBAR is still at its default location of
0x4000_0000, the source register would be loaded with 0x4400_0000.
Backdoor access to Flash for reads can be made by the bus master, but it
takes 2 cycles longer than a direct read of the Flash if using its FLASHBAR
address.
The Flash is marked as valid on reset based on the RCON (reset
configuration) pin state. Flash space is valid on reset when booting in single
chip mode (RCON pin asserted and D[26]/D[17]/D[16] set to 110), or when
booting internally in master mode (RCON asserted and D[26]/D[17]/D[16]
are set to 111 and D[18] and D[19] are set to 00). See
Configuration Module
configuration is not overriden, the device (by default) boots in single chip
mode and the Flash space will be marked as valid at address 0x0. The Flash
configuration field is checked during the reset sequence to see if the Flash
is secured. If it is the part will always boot from internal Flash, since it will
be marked as valid, regardless of what is done for chip configuration.
31
15
30
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 6-3. Flash Base Address Register (FLASHBAR)
29
—
28
27
(CCM)”).
(CCM)” for more details. When the default reset
R
26
0000_0001_0010_000
0000_0000_0000_0000
25
9
NOTE
NOTE
CPU + 0xC04
WP
24
8
R/W
23
7
—
22
6
C/I
21
5
Chapter 27, “Chip
SC
20
4
SD
19
3
R/W
Freescale Semiconductor
UC
18
2
Chapter 27,
UD
—
1
Note
See
16
V
0
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