MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 298

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

DMA Controller Module
16.1.1
The DMA controller module features are as follows:
16.2
The DMAREQC register provides a software-controlled connection matrix for DMA requests. It logically
routes DMA requests from the DMA timers and UARTs to the four channels of the DMA controller.
Writing to this register determines the exact routing of the DMA request to the four channels of the DMA
modules. If DCRn[EEXT] is set and the channel is idle, the assertion of the appropriate DREQn activates
channel n.
16-2
•
•
•
•
•
•
•
•
Bits
Reset
Reset
Field
Field
R/W
R/W
Four independently programmable DMA controller channels
Auto-alignment feature for source or destination accesses
Dual-address transfers
Channel arbitration on transfer boundaries
Data transfers in 8-, 16-, 32-, or 128-bit blocks using a 16-byte buffer
Continuous-mode or cycle-steal transfers
Independent transfer widths for source and destination
Independent source and destination address registers
DMA Request Control (DMAREQC)
DMA Module Features
Name
31
15
Throughout this chapter “external request” and DREQ are used to refer to a
DMA request from one of the on-chip UARTS or DMA timers. For details
on the connections associated with DMA request inputs, see
“DMA Request Control
DMAC3
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 16-2. DMA Request Control Register (DMAREQC)
12
Table 16-1. DMAREQC Field Description
11
(DMAREQC).”
DMAC2
—
0000_0000_0000_0000
0000_0000_0000_0000
IPSBAR + 0x014
NOTE
8
R/W
R/W
Description
7
DMAC1
20
4
Section 16.2,
19
3
Freescale Semiconductor
DMAC0
—
16
0