MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 707
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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33.13.3 MII Async Inputs Signal Timing (ECRS and ECOL)
Table 33-23
Figure 33-13
33.13.4 MII Serial Management Channel Timing (EMDIO and EMDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
management channel timings.
Figure 33-14
Freescale Semiconductor
1
ECOL has the same timing in 10 Mbit 7-wire interface mode.
Num
M9
1
M10
M11
M12
M13
M14
M15
Num
ETXD[3:0] (outputs)
lists MII asynchronous inputs signal timing.
ECRS, ECOL minimum pulse width
ETXCLK (input)
shows MII asynchronous input timings listed in
shows MII serial management channel timings listed in
EMDC falling edge to EMDIO output invalid (minimum propagation
delay)
EMDC falling edge to EMDIO output valid (max prop delay)
EMDIO (input) to EMDC rising edge setup
EMDIO (input) to EMDC rising edge hold
EMDC pulse width high
EMDC pulse width low
ETXEN
ETXER
ECRS, ECOL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 33-24. MII Serial Management Channel Timing
Figure 33-12. MII Transmit Signal Timing Diagram
Figure 33-13. MII Async Inputs Timing Diagram
Table 33-23. MII Async Inputs Signal Timing
Characteristic
Characteristic
M5
M6
M7
M9
Table
M8
Min
1.5
33-23.
Table
40% 60% MDC period
40% 60% MDC period
Min
10
—
33-24.
0
0
Max
—
Table 33-24
Max
25
—
—
—
Electrical Characteristics
ETXCLK period
Unit
ns
ns
ns
ns
lists MII serial
Unit
33-23
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