MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 81
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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3.2
The following table and sections explain the MAC registers:
3.2.1
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
Freescale Semiconductor
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BDM: 0x804 (MACSR)
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see
0x80A
0x80B
BDM
0x804
0x805
0x806
0x807
0x808
0x809
31–12
W
PAVn
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Field
11–8
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
1
Memory Map/Register Definition
MAC Status Register (MACSR)
MAC Status Register (MACSR)
MAC Address Mask Register (MASK)
MAC Accumulator 0 (ACC0)
MAC Accumulator 0,1 Extension Bytes (ACCext01)
MAC Accumulator 2,3 Extension Bytes (ACCext23)
MAC Accumulator 1 (ACC1)
MAC Accumulator 2 (ACC2)
MAC Accumulator 3 (ACC3)
Reserved, must be cleared.
Product/accumulation overflow flags. Contains four flags, one per accumulator, that indicate if past MAC or
MSAC instructions generated an overflow during product calculation or the 48-bit accumulation. When a
MAC or MSAC instruction is executed, the PAVn flag associated with the destination accumulator forms the
general overflow flag, MACSR[V]. Once set, each flag remains set until V is cleared by a move.l, MACSR
instruction or the accumulator is loaded directly.
Bit 11: Accumulator 3
...
Bit 8: Accumulator 0
Chapter 43, “Debug Module.”
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 3-2. MAC Status Register (MACSR)
Register
Table 3-2. MACSR Field Descriptions
Table 3-1. EMAC Memory Map
Description
Width
(bits)
32
32
32
32
32
32
32
32
PAVn
Access
Enhanced Multiply-Accumulate Unit (EMAC)
8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OMC S/U
0
7
0xFFFF_FFFF
0x0000_0000
Reset Value
Undefined
Undefined
Undefined
Undefined
Undefined
Undefined
0
6
Access: Supervisor read/write
F/I
0
5
R/T N
0
4
Section/Page
BDM read/write
0
3.2.1/3-3
3.2.2/3-5
3.2.3/3-6
3.2.4/3-7
3.2.4/3-7
3.2.3/3-6
3.2.3/3-6
3.2.3/3-6
3
Z
0
2
V EV
0
1
3-3
0
0
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