MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 645

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Command Sequence:
Operand Data
Result Data
30.5.3.3.5
DUMP
set up the starting address of the block and to retrieve the first result. If an initial
before the first
operands. The initial address is incremented by the operand size (1, 2, or 4) and saved in a temporary
register. Subsequent
current operand size, and store the updated address in the temporary register.
Freescale Semiconductor
WRITE (LONG)
WRITE (B/W)
is used with the
???
???
Dump Memory Block (
DUMP
, an illegal command response is returned. The
’NOT READY’
’NOT READY’
DUMP
MS ADDR
MS ADDR
READ
This two-operand instruction requires a longword absolute address that specifies
a location to which the data operand is to be written. Byte data is sent as a 16-bit
word, justified in the LSB; 16- and 32-bit operands are sent as 16 and 32 bits,
respectively
Command complete status is indicated by returning 0xFFFF (with S cleared)
when the register write is complete. A value of 0x0001 (with S set) is returned if
a bus error occurs.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
commands use this address, perform the memory read, increment it by the
command to access large blocks of memory. An initial
Figure 30-24. WRITE Command Sequence
’NOT READY’
’NOT READY’
LS ADDR
LS ADDR
DUMP
)
’NOT READY’
’NOT READY’
MS DATA
’NOT READY’
DATA
LS DATA
DUMP
LOCATION
MEMORY
WRITE
LOCATION
MEMORY
WRITE
command retrieves subsequent
’CMD COMPLETE’
READ
’NOT READY’
’CMD COMPLETE’
’NOT READY’
READ
NEXT CMD
BERR
NEXT CMD
XXX
XXX
BERR
XXX
XXX
’NOT READY’
’NOT READY’
NEXT CMD
is not executed
NEXT CMD
is executed to
Debug Support
30-27