MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 322
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 322 of 766
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Fast Ethernet Controller (FEC)
17.4.5
The TDAR is a command register which the user writes to indicate the transmit descriptor ring is updated
(transmit buffers have been produced by the driver with the ready bit set in the buffer descriptor).
When the register is written, the TDAR bit is set. This value is independent of the data actually written by
the user. When set, the FEC polls the transmit descriptor ring and processes transmit frames (provided
ECR[ETHER_EN] is also set). After the FEC polls a transmit descriptor that is a ready bit not set, FEC
clears the TDAR bit and ceases transmit descriptor ring polling until the user sets the bit again, signifying
additional descriptors are placed into the transmit descriptor ring.
The TDAR register is cleared at reset, when ECR[ETHER_EN] is cleared, or when ECR[RESET] is set.
17.4.6
ECR is a read/write user register, though hardware may alter fields in this register as well. The ECR
enables/disables the FEC.
17-12
31–25
RDAR
31–25
TDAR
Field
Field
23–0
23–0
24
24
IPSBAR
Offset:
Reset 0 0 0 0 0 0 0
Reserved, must be cleared.
Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional
empty descriptors remain in the receive ring. Also cleared when ECR[ETHER_EN] is cleared.
Reserved, must be cleared.
W
Reserved, must be cleared.
Set to 1 when this register is written, regardless of the value written. Cleared by the FEC device when no additional
ready descriptors remain in the transmit ring. Also cleared when ECR[ETHER_EN] is cleared.
Reserved, must be cleared.
R 0 0 0 0 0 0 0
Transmit Descriptor Active Register (TDAR)
Ethernet Control Register (ECR)
0x1014
31 30 29 28 27 26 25
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Figure 17-5. Transmit Descriptor Active Register (TDAR)
TDAR
24
0
Table 17-7. RDAR Field Descriptions
Table 17-8. TDAR Field Descriptions
23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Description
Description
8
7
Access: User read/write
6
Freescale Semiconductor
5
4
3
2
1
0
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