MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 442
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 442 of 766
- Download datasheet (9Mb)
UART Modules
programming the ERR bit in the UART’s mode register (UMR1n), status is provided in character or block
modes.
USRn[RXRDY] is set when at least one character is available to be read by the CPU. A read of the receive
buffer produces an output of data from the top of the FIFO. After the read cycle, the data at the top of the
FIFO and its associated status bits are popped and the receiver shift register can add new data at the bottom
of the FIFO. The FIFO-full status bit (FFULL) is set if all three positions are filled with data. The RXRDY
or FFULL bit can be selected to cause an interrupt and TXRDY or RXRDY can be used to generate a DMA
request.
The two error modes are selected by UMR1n[ERR]:
In either mode, reading the USRn does not affect the FIFO. The FIFO is popped only when the receive
buffer is read. The USRn should be read before reading the receive buffer. If all three receiver holding
registers are full, a new character is held in the receiver shift register until space is available. However, if
a second new character is received, the contents of the character in the receiver shift register is lost, the
FIFOs are unaffected, and USRn[OE] is set when the receiver detects the start bit of the new overrunning
character.
To support flow control, the receiver can be programmed to automatically negate and assert URTSn, in
which case the receiver automatically negates URTSn when a valid start bit is detected and the FIFO is
full. The receiver asserts URTSn when a FIFO position becomes available; therefore, connecting URTSn
to the UCTSn input of the transmitting device can prevent overrun errors.
23.4.3
The UART can be configured to operate in various looping modes. These modes are useful for local and
remote system diagnostic functions. The modes are described in the following paragraphs and in
Section 23.3, “Memory Map/Register Definition.”
The UART’s transmitter and receiver should be disabled when switching between modes. The selected
mode is activated immediately upon mode selection, regardless of whether a character is being received
or transmitted.
23-22
•
•
In character mode (UMR1n[ERR] = 0), status is given in the USRn for the character at the top of
the FIFO.
In block mode, the USRn shows a logical OR of all characters reaching the top of the FIFO since
the last RESET ERROR STATUS command. Status is updated as characters reach the top of the
FIFO. Block mode offers a data-reception speed advantage where the software overhead of
error-checking each character cannot be tolerated. However, errors are not detected until the check
is performed at the end of an entire message—the faulting character is not identified.
Looping Modes
The receiver continues reading characters in the FIFO if the receiver is
disabled. If the receiver is reset, the FIFO, URTSn control, all receiver status
bits, interrupts, and DMA requests are reset. No more characters are
received until the receiver is reenabled.
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
NOTE
Freescale Semiconductor
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