MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 412
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- Current page: 412 of 766
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Queued Serial Peripheral Interface (QSPI)
22.3.6
The QDR is used to access QSPI RAM indirectly. The CPU reads and writes all data from and to the QSPI
RAM through this register.
A write to QDR causes data to be written to the RAM entry specified by QAR[ADDR]. This also causes
the value in QAR to increment. Correspondingly, a read at QDR returns the data in the RAM at the address
specified by QAR[ADDR]. This also causes QAR to increment. A read access requires a single wait state.
22.3.7
The command RAM is accessed using the upper byte of the QDR; the QSPI cannot modify information in
command RAM. There are 16 bytes in the command RAM. Each byte is divided into two fields. The chip
select field enables external peripherals for transfer. The command field provides transfer operations.
22-8
IPSBAR
IPSBAR
ADDR
Offset:
DATA
Field
15–6
Field
15–0
Offset:
Reset
5–0
Reset
W
R
W
R
0x00_0350 (QAR)
0x00_0354 (QDR)
Reserved, must be cleared.
Address used to read/write the QSPI RAM. Ranges are as follows:
0x00–0x0F Transmit RAM
0x10–0x1F Receive RAM
0x20–0x2F Command RAM
0x30–0x3F Reserved
A write to this field causes data to be written to the QSPI RAM entry specified by QAR[ADDR]. Similarly, a read of
this field returns the data in the QSPI RAM at the address specified by QAR[ADDR]. During command RAM
accesses (QAR[ADDR] = 0x20–0x2F), only the most significant byte of this field is used.
15
15
0
0
0
QSPI Data Register (QDR)
Command RAM Registers (QCR0–QCR15)
14
0
14
0
0
13
0
13
0
0
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
12
0
12
0
0
Figure 22-7. QSPI Address Register (QAR)
Figure 22-8. QSPI Data Register (QDR)
11
0
Table 22-8. QDR Field Descriptions
Table 22-7. QAR Field Descriptions
11
0
0
10
0
10
0
0
0
9
9
0
0
Description
Description
0
8
DATA
0
0
8
0
7
0
0
7
0
6
0
0
6
0
5
0
5
0
4
0
4
0
3
Freescale Semiconductor
Access: User read/write
Access: User read/write
3
0
ADDR
0
2
0
2
0
1
1
0
0
0
0
0
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