MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 66

• Manufacturer Part Number: MCF5282CVF80J
• Description: IC MPU 512K FLASH 256MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF528xr

Specifications of MCF5282CVF80J

• Core Processor: Coldfire V2
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 150
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-MAPBGA
• Processor Series: MCF528x
• Core: ColdFire V2
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: NNDK-MOD5282-KIT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

ColdFire Core
In the original M68000 ISA definition, lines A and F were effectively reserved for user-defined operations
(line A) and co-processor instructions (line F). Accordingly, there are two unique exception vectors
associated with illegal opwords in these two lines.
Any attempted execution of an illegal 16-bit opcode (except for line-A and line-F opcodes) generates an
illegal instruction exception (vector 4). Additionally, any attempted execution of any non-MAC line-A and
most line-F opcodes generate their unique exception types, vector numbers 10 and 11, respectively.
ColdFire cores do not provide illegal instruction detection on the extension words on any instruction,
including MOVEC.
2.3.4.4
Attempting to divide by zero causes an exception (vector 5, offset equal 0x014).
2.3.4.5
The attempted execution of a supervisor mode instruction while in user mode generates a privilege
violation exception. See ColdFire Programmer’s Reference Manual for a list of supervisor-mode
instructions.
There is one special case involving the HALT instruction. Normally, this opcode is a supervisor mode
instruction, but if the debug module's CSR[UHE] is set, then this instruction can be also be executed in
user mode for debugging purposes.
2.3.4.6
To aid in program development, all ColdFire processors provide an instruction-by-instruction tracing
capability. While in trace mode, indicated by setting of the SR[T] bit, the completion of an instruction
execution (for all but the stop instruction) signals a trace exception. This functionality allows a debugger
to monitor program execution.
The stop instruction has the following effects:
2-20
Opword[Line]
1. The instruction before the stop executes and then generates a trace exception. In the exception stack
2. When the trace handler is exited, the stop instruction executes, loading the SR with the immediate
0xC
0xD
0xA
0xB
0xE
0xF
frame, the PC points to the stop opcode.
operand from the instruction.
Divide-By-Zero
Privilege Violation
Trace Exception
EMAC, Move 3-bit Quick (MOV3Q)
Compare (CMP), Exclusive-OR (EOR)
Logical AND (AND), Multiply Word (MUL)
Add (ADD), Add Extended (ADDX)
Arithmetic and logical shifts (ASL, ASR, LSL, LSR)
Cache Push (CPUSHL), Write DDATA (WDDATA), Write Debug (WDEBUG)
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
Table 2-8. ColdFire Opword Line Definition (continued)
Instruction Class
Freescale Semiconductor