MCF5282CVF80J Freescale Semiconductor, MCF5282CVF80J Datasheet - Page 279
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MCF5282CVF80J
Manufacturer Part Number
MCF5282CVF80J
Description
IC MPU 512K FLASH 256MAPBGA
Manufacturer
Freescale Semiconductor
Series
MCF528xr
Datasheet
1.MCF5216CVM66J.pdf
(766 pages)
Specifications of MCF5282CVF80J
Core Processor
Coldfire V2
Core Size
32-Bit
Speed
80MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
150
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
64K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
256-MAPBGA
Processor Series
MCF528x
Core
ColdFire V2
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
NNDK-MOD5282-KIT
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MCF5282CVF80J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Freescale Semiconductor
10–8
5–4
2–0
Bit
7
6
3
Name
IMRS Initiate mode register set (
CBM Command and bank MUX [2:0]. Because different SDRAM configurations cause the command and
PS
—
IP
—
bank select lines to correspond to different addresses, these resources are programmable. CBM
determines the addresses onto which these functions are multiplexed.
Note: It is important to set CBM according to the location of the command bit.
This encoding and the address multiplexing scheme handle common SDRAM organizations. Bank
select bits include a base bit and all address bits above for SDRAMs with multiple bank select bits.
Reserved, should be cleared.
SDRAMs. In initialization, IMRS should be set only after all DRAM controller registers are initialized
and
block programs the SDRAM’s mode register. Thus, the address of the access should be programmed
to place the correct mode information on the SDRAM address pins. Because the SDRAM does not
register this information, it doesn’t matter if the IMRS access is a read or a write or what, if any, data is
put onto the data bus. The DRAM controller clears IMRS after the
0 Take no action
1 Initiate
Port size. Indicates the port size of the associated block of SDRAM, which allows for dynamic sizing of
associated SDRAM accesses. PS functions the same in asynchronous operation.
00 32-bit port
01 8-bit port
1x 16-bit port
Initiate precharge all (
finished. Accesses via IP should be no wider than the port size programmed in PS.
0 Take no action.
1 A
Reserved, should be cleared.
executed after all DRAM controller registers are programmed. After IP is set, the next write to an
appropriate SDRAM address generates the
PALL
PALL
MCF5282 and MCF5216 ColdFire Microcontroller User’s Manual, Rev. 3
and
MRS
command is sent to the associated SDRAM block. During initialization, this command is
Table 15-5. DACRn Field Descriptions (continued)
REFRESH
command
PALL
commands have been issued. After IMRS is set, the next access to an SDRAM
MRS
) command. The DRAM controller clears IP after the
CBM
101
110
111
000
001
010
011
100
) command. Setting IMRS generates a
Command Bit
Description
PALL
17
18
19
20
21
22
23
24
command to the SDRAM block.
Bank Select Bits
18 and up
19 and up
20 and up
21 and up
22 and up
23 and up
24 and up
25 and up
MRS
Synchronous DRAM Controller Module
MRS
command finishes.
command to the associated
PALL
command is
15-7
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