HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 10

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.4
Section 5 Exception Processing
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Section 6 Interrupt Controller (INTC)
6.1
6.2
Rev. 5.00 Jan 06, 2006 page viii of xx
Notes on Using.................................................................................................................. 58
Overview........................................................................................................................... 61
5.1.1
5.1.2
5.1.3
Resets ................................................................................................................................ 65
5.2.1
Address Errors .................................................................................................................. 66
5.3.1
5.3.2
Interrupts ........................................................................................................................... 67
5.4.1
5.4.2
5.4.3
Exceptions Triggered by Instructions ............................................................................... 69
5.5.1
5.5.2
5.5.3
5.5.4
When Exception Sources Are Not Accepted .................................................................... 71
5.6.1
5.6.2
Stack Status after Exception Processing Ends .................................................................. 72
Notes on Use ..................................................................................................................... 73
5.8.1
5.8.2
5.8.3
Overview........................................................................................................................... 75
6.1.1
6.1.2
6.1.3
6.1.4
Interrupt Sources............................................................................................................... 78
6.2.1
6.2.2
6.2.3
6.2.4
Types of Exception Processing and Priority ........................................................ 61
Exception Processing Operations......................................................................... 62
Exception Processing Vector Table ..................................................................... 63
Power-On Reset ................................................................................................... 65
Address Error Sources ......................................................................................... 66
Address Error Exception Processing.................................................................... 67
Interrupt Sources.................................................................................................. 67
Interrupt Priority Level ........................................................................................ 68
Interrupt Exception Processing ............................................................................ 68
Types of Exceptions Triggered by Instructions ................................................... 69
Trap Instructions .................................................................................................. 69
Illegal Slot Instructions ........................................................................................ 70
General Illegal Instructions.................................................................................. 70
Immediately after a Delayed Branch Instruction ................................................. 71
Immediately after an Interrupt-Disabled Instruction............................................ 71
Value of Stack Pointer (SP) ................................................................................. 73
Value of Vector Base Register (VBR) ................................................................. 73
Address Errors Caused by Stacking of Address Error Exception Processing ...... 73
Features................................................................................................................ 75
Block Diagram ..................................................................................................... 76
Pin Configuration................................................................................................. 77
Register Configuration......................................................................................... 77
NMI Interrupts ..................................................................................................... 78
User Break Interrupt ............................................................................................ 78
IRQ Interrupts ...................................................................................................... 78
On-Chip Peripheral Module Interrupts ................................................................ 79
....................................................................................... 61
........................................................................... 75