HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 742

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A On-Chip Supporting Module Registers
Timer Status Register AL (TSRAL)
Note:
Bit
4
3
2
1
0
Rev. 5.00 Jan 06, 2006 page 720 of 818
REJ09B0273-0500
Initial value:
* Only 0 can be written to clear the flag.
Bit name:
Bit Name
Overflow flag
(OVF0)
Input capture flag
(ICF0D)
Input capture flag
(ICF0C)
Input capture flag
(ICF0B)
Input capture flag
(ICF0A)
R/W:
Bit:
—
R
7
0
Value
0
1
0
1
0
1
0
1
0
1
—
R
6
0
Description
[Clearing condition]
Read OVF0 when OVF0 =1, then write 0 in OVF0
[Setting condition]
TCNT0 overflowed from H'FFFFFFFF to H'00000000
[Clearing condition]
Read ICF0D when ICF0D =1, then write 0 in ICF0D
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0D by an input capture signal
[Clearing condition]
Read ICF0C when ICF0C =1, then write 0 in ICF0C
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0C by an input capture signal
[Clearing conditions]
1. Read ICF0B when ICF0B =1, then write 0 in ICF0B
2. When cleared by the DMAC in data transfer
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0B by an input capture signal
[Clearing condition]
Read ICF0A when ICF0A =1, then write 0 in ICF0A
[Setting condition]
TCNT0 value is transferred to input capture register
ICR0A by an input capture signal
—
R
5
0
H'FFFF8285 (Channel 0)
R/(W) *
OVF0
4
0
R/(W) *
ICF0D
3
0
R/(W) *
ICF0C
2
0
8
R/(W) *
ICF0B
1
0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
(Initial value)
R/(W) *
ICF0A
ATU
0
0