HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 305

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

10.3
10.3.1
The ATU has eleven timers of seven kinds in channels 0 to 10. It also has a built-in prescaler that
generates input clocks, and it is possible to generate or select internal clocks of the required
frequency independently of circuitry outside the ATU.
The operation of each channel and the prescaler is outlined below.
Channel 0 (32-Bit Dedicated Input Capture Timer): Channel 0 has a 32-bit free-running
counter (TCNT0) and four 32-bit input capture registers (ICR0A to ICR0D). TCNT0 is an up-
counter that performs free-running operation. The four input capture registers (ICR0A to ICR0D)
can be used for input capture with input from the corresponding external signal input pin (TIA0 to
TID0) or output compare-match trigger input from channel 1 GR1A. Input pin (TIA0 to TID0) and
GR1A output compare-match trigger selection can be made by setting the trigger selection register
(TGSR).
Channel 0 also has an interval interrupt request register (ITVRR). When 1 is set in ITVE0 to
ITVE3 in ITVRR, an interval timer function can be used whereby an interrupt request can be sent
to the CPU when the corresponding bit (of bits 10 to 13) in TCNT0 changes to 1.
Channels 1 and 2: ATU channel 1 has a 16-bit free-running counter (TCNT1) and six 16-bit
general registers (GR1A to GR1F). TCNT1 is an up-counter that performs free-running operation.
The six general registers (GR1A to GR1F) can be used as input capture or output compare-match
registers using the corresponding external signal I/O pin (TIOA0 to TIOF0). Use as a one-shot
pulse offset function is also possible in combination with ATU channel 10 described below.
Channel 2 has a 16-bit free-running counter (TCNT2) and two 16-bit general registers (GR2A and
GR2B). Channel 2 can perform the same kind of operations as channel 1, the only difference being
in the number of general registers.
In addition, channel 1 has a 16-bit dedicated input capture register (OSBR) (not provided in
channel 2). The TIA0 external pin for input to channel 0 can also be used as the OSBR trigger
input, enabling use of a twin-capture function.
Operation
Overview
Rev. 5.00 Jan 06, 2006 page 283 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500