HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 129

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.5
7.5.1
Two instructions are simultaneously fetched from on-chip memory. If a break condition is set on
the second of these two instructions but the contents of the UBC break condition registers are
changed so as to alter the break condition immediately after the first of the two instructions is
fetched, a user break interrupt will still occur when the second instruction is fetched.
7.5.2
When a conditional branch instruction or TRAPA instruction causes a branch, instructions are
fetched and executed as follows:
1. Conditional branch instruction, branch taken: BT, BF
2. When branching with a delayed conditional instruction: BT/S and BF/S instructions
TRAPA instruction, branch taken: TRAPA
When a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination will be fetched after the next instruction or the one after that does an overrun fetch.
However, because the instruction that is the object of the break first breaks after a definite
instruction fetch and execution, the kind of overrun fetch instructions noted above do not
become objects of a break. If data access breaks are also included with instruction fetch breaks
as break conditions, a break occurs because the instruction overrun fetch is also regarded as
becoming a data break.
Instruction fetch cycles: Conditional branch fetch
Instruction execution: Conditional branch instruction execution
instruction execution
Instruction fetch order: Corresponding instruction fetch
slot)
Instruction execution order: Corresponding instruction execution
execution
On-Chip Memory Instruction Fetch
Instruction Fetch at Branches
Cautions on Use
Next-instruction overrun fetch
overrun fetch of instruction after next
branch destination instruction execution
Branch destination fetch
branch destination instruction fetch
Rev. 5.00 Jan 06, 2006 page 107 of 818
Section 7 User Break Controller (UBC)
Next-instruction overrun fetch
next instruction fetch (delay
Branch destination
delay slot instruction
REJ09B0273-0500