HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 176

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 9 Direct Memory Access Controller (DMAC)
Table 9.4
RS3 RS2 RS1 RS0
0
1
ATU:
SCI0, SCI1, SCI2: Serial communication interface channels 0–2
ADDR0, ADDR1:
Note:
Rev. 5.00 Jan 06, 2006 page 154 of 818
REJ09B0273-0500
1
0
1
* External memory, memory-mapped external device, on-chip memory, on-chip
1
0
1
0
1
peripheral module (excluding DMAC, BSC, and UBC)
Selecting On-Chip Peripheral Module Request Modes with the RS Bits
0
1
0
1
0
1
0
1
0
1
Advanced timer unit
A/D converter channel 0 and 1 A/D registers
DMAC Transfer
Request Source
ATU
ATU
SCI0 transmit
block
SCI0 receive
block
SCI1 transmit
block
SCI1 receive
block
SCI2 transmit
block
SCI2 receive
block
A/D converter
A/D converter
DMAC Transfer
Request Signal
Compare-match
6 generation
Input capture B
generation
TXI0 (SCI0
transmit-data-
empty transfer
request)
RXI0 (SCI0
receive-data-full
transfer request)
TXI1 (SCI1
transmit-data-
empty transfer
request)
RXI1 (SCI1
receive-data-full
transfer request)
TXI2 (SCI2
transmit-data-
empty transfer
request)
RXI2 (SCI2
receive-data-full
transfer request)
ADI (A/D
conversion end
interrupt)
ADI (A/D
conversion end
interrupt)
Transfer
Source
Don’t care * Don’t care * Burst/cycle
Don’t care * Don’t care * Burst/cycle
Don’t care * TDR0
RDR0
Don’t care * TDR1
RDR1
Don’t care * TDR2
RDR2
ADDR0
ADDR1
Transfer
Destination Bus Mode
Don’t care * Burst/cycle
Don’t care * Burst/cycle
Don’t care * Burst/cycle
Don’t care * Burst/cycle
Don’t care * Burst/cycle
steal
steal
Burst/cycle
steal
steal
Burst/cycle
steal
steal
Burst/cycle
steal
steal
steal
steal