HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 169

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 5—Transfer Mode (TM): Specifies the bus mode for data transfer.
Bits 4 and 3—Transfer Size 1, 0 (TS1, TS0): Specifies size of data for transfer.
Bit 2—Interrupt Enable (IE): When this bit is set to 1, interrupt requests are generated after the
number of data transfers specified in the DMATCR (when TE = 1).
Bit 1—Transfer End (TE): This bit is set to 1 after the number of data transfers specified by the
DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated.
If data transfer ends before TE is set to 1 (for example, due to an NMI or address error, or clearing
of the DE bit or DME bit of the DMAOR) the TE is not set to 1. With this bit set to 1, data transfer
is disabled even if the DE bit is set to 1.
Bit 5: TM
0
1
Bit 4: TS1
0
0
1
1
Bit 2: IE
0
1
Bit 1: TE
0
1
Bit 3: TS0
0
1
0
1
Description
Interrupt request not generated after DMATCR-specified transfer count
(initial value)
Interrupt request enabled on completion of DMATCR specified number
of transfers
Description
DMATCR-specified transfer count not ended (initial value)
Clear condition: 0 write after TE = 1 read, Power-on reset, standby
mode
DMATCR specified number of transfers completed
Description
Cycle steal mode (initial value)
Burst mode
Description
Specifies byte size (8 bits) (initial value)
Specifies word size (16 bits)
Specifies longword size (32 bits)
Prohibited
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 Jan 06, 2006 page 147 of 818
REJ09B0273-0500