HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 140

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus State Controller (BSC)
Bits 7–4—Idle Specification for Continuous Access (CW3, CW2, CW1, CW0): The
continuous access idle specification makes insertions to clearly delineate the bus intervals by once
negating the CSn signal when doing consecutive accesses of the same CS space. When a write
immediately follows a read, the number of idle cycles inserted is the larger of the two values
specified by IW and CW. Refer to section 8.4, Waits between Access Cycles, for details.
CW3 specifies the continuous access idles for CS3 space; CW2 specifies the continuous access
idles for CS2 space; CW1 specifies the continuous access idles for CS1 space and CW0 specifies
the continuous access idles for CS0 space.
Bit 7: CW3
0
1
Bit 6: CW2
0
1
Bit 5: CW1
0
1
Bit 4: CW0
0
1
Bits 3–0—CS
extension specification is for making insertions to prevent extension of the RD signal or WRx
signal assert period beyond the length of the CSn signal assert period. Extended cycles insert one
cycle before and after each bus cycle, which simplifies interfaces with external devices and also
has the effect of extending write data hold time. Refer to section 8.3.3 CS Assert Period Extension
for details.
SW3 specifies the CS assert extension for CS3 space access; SW2 specifies the CS assert
extension for CS2 space access; SW1 specifies the CS assert extension for CS1 space access and
SW0 specifies the CS assert extension for CS0 space access.
Rev. 5.00 Jan 06, 2006 page 118 of 818
REJ09B0273-0500
CS Assert Extension Specification (SW3, SW2, SW1, SW0): The CS assert cycle
CS
CS
Description
No CS3 space continuous access idle cycles
One CS3 space continuous access idle cycle (initial value)
Description
No CS2 space continuous access idle cycles
One CS2 space continuous access idle cycle (initial value)
Description
No CS1 space continuous access idle cycles
One CS1 space continuous access idle cycle (initial value)
Description
No CS0 space continuous access idle cycles
One CS0 space continuous access idle cycle (initial value)