HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 171

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 9–8—Priority Mode 1 and 0 (PR1 and PR0): These bits determine the priority level of
channels for execution when transfer requests are made for several channels simultaneously.
Bit 2—Address Error Flag (AE): Indicates that an address error has occurred during DMA
transfer. If this bit is set during a data transfer, transfers on all channels are suspended. The CPU
cannot write a 1 to the AE bit. Clearing is effected by 0 write after 1 read.
Bit 1—NMI Flag (NMIF): Indicates input of an NMI. This bit is set irrespective of whether the
DMAC is operating or suspended. If this bit is set during a data transfer, transfers on all channels
are suspended. The CPU is unable to write a 1 to the NMIF. Clearing is effected by 0 write after 1
read.
Bit 0—DMAC Master Enable (DME): This bit enables activation of the entire DMAC. When
the DME bit and DE bit of the CHCR for the corresponding channel are set to 1, that channel is
transfer-enabled. If this bit is cleared during a data transfer, transfers on all channels are
suspended.
Bit 9: PR1
0
0
1
1
Bit 2: AE
0
1
Bit 1: NMIF
0
1
Bit 8: PR0
0
1
0
1
Description
No address error, DMA transfer enabled (initial value)
Clearing condition: Write AE = 0 after reading AE = 1
Address error, DMA transfer disabled
Setting condition: Address error due to DMAC
Description
No NMI interrupt, DMA transfer enabled (initial value)
Clearing condition: Write NMIF = 0 after reading NMIF = 1
NMI has occurred, DMC transfer prohibited
Set condition: NMI interrupt occurrence
Description
CH0
CH0
CH2
Round robin mode
CH1
CH2
CH0
Section 9 Direct Memory Access Controller (DMAC)
CH2
CH3
CH1
CH3 (initial value)
CH1
CH3
Rev. 5.00 Jan 06, 2006 page 149 of 818
REJ09B0273-0500