HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 302

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
OSBR is connected to the CPU via an internal 16-bit bus, and can only be accessed by a word
read.
OSBR is initialized to H'0000 by a power-on reset, and in hardware standby mode and software
standby mode.
For details, see sections 10.3.4, Input Capture Function.
10.2.17 Cycle Registers (CYLR)
The cycle registers (CYLR) are 16-bit registers. The ATU has four cycle registers, one each for
channels 6 to 9.
Channel
6
7
8
9
Cycle Registers (CYLR6 to CYLR9)
The CYLR registers are 16-bit readable/writable registers used for PWM cycle storage.
The CYLR value is constantly compared with the corresponding free-running counter (TCNT6 to
TCNT9) value, and when the two values match, the corresponding timer start register (TSR) bit
(CMF6 to CMF9) is set to 1, and the free-running counter (TCNT6 to TCNT9) is cleared. At the
same time, the buffer register (BFR) value is transferred to the duty register (DTR).
The CYLR registers are connected to the CPU via an internal 16-bit bus, and can only be accessed
by a word read or write.
The CYLR registers are initialized to H'FFFF by a power-on reset, and in hardware standby mode
and software standby mode.
For details of the CYLR, BFR, and DTR registers, see sections 10.3.9, PWM Timer Function.
Rev. 5.00 Jan 06, 2006 page 280 of 818
REJ09B0273-0500
Initial value:
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit:
Abbreviation
CYLR6
CYLR7
CYLR8
CYLR9
15
1
14
1
13
1
12
1
Function
Cycle registers
11
1
10
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
1

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