HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 450

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
The receive margin in the asynchronous mode can therefore be expressed as:
From the equation above, if F = 0 and D = 0.5 the receive margin is 46.875%:
This is a theoretical value. A reasonable margin to allow in system designs is 20–30%.
Rev. 5.00 Jan 06, 2006 page 428 of 818
REJ09B0273-0500
Synchronization
sampling timing
sampling timing
data (RxD)
base clock
M = 0.5
M : Receive margin (%)
N : Ratio of clock frequency to bit rate (N = 16)
D : Clock duty cycle (D = 0–1.0)
L : Frame length (L = 9–12)
F : Absolute deviation of clock frequency
D = 0.5, F = 0
M = (0.5 – 1/(2
Receive
Internal
Figure 13.23 Receive Data Sampling Timing in Asynchronous Mode
= 46.875%
Data
(
0
2N
1
8 clocks
Start bit
)
16))
(L
16 clocks
0.5) F
100%
7 8
–7.5 clocks
D
N
0.5
15 0
(1
+7.5 clocks
F)
100%
D0
7 8
15 0
D1
5