HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 17

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

14.5 Interrupt Sources and DMA Transfer Requests ................................................................ 456
14.6 Usage Notes ...................................................................................................................... 456
Section 15 Compare Match Timer (CMT)
15.1 Overview........................................................................................................................... 459
15.2 Register Descriptions ........................................................................................................ 462
15.3 Operation .......................................................................................................................... 465
15.4 Interrupts ........................................................................................................................... 466
15.5 Notes on Use ..................................................................................................................... 469
Section 16 Pin Function Controller (PFC)
16.1 Overview........................................................................................................................... 473
16.2 Register Configuration...................................................................................................... 478
16.3 Register Descriptions ........................................................................................................ 479
14.4.6 ADEND Output Pin ............................................................................................. 455
15.1.1 Features................................................................................................................ 459
15.1.2 Block Diagram ..................................................................................................... 460
15.1.3 Register Configuration......................................................................................... 461
15.2.1 Compare Match Timer Start Register (CMSTR) ................................................. 462
15.2.2 Compare Match Timer Control/Status Register (CMCSR) ................................. 463
15.2.3 Compare Match Timer Counter (CMCNT) ......................................................... 464
15.2.4 Compare Match Timer Constant Register (CMCOR).......................................... 465
15.3.1 Period Count Operation ....................................................................................... 465
15.3.2 CMCNT Count Timing........................................................................................ 466
15.4.1 Interrupt Sources and DTC Activation ................................................................ 466
15.4.2 Compare Match Flag Set Timing......................................................................... 467
15.4.3 Compare Match Flag Clear Timing ..................................................................... 468
15.5.1 Contention between CMCNT Write and Compare Match................................... 469
15.5.2 Contention between CMCNT Word Write and Incrementation .......................... 470
15.5.3 Contention between CMCNT Byte Write and Incrementation ............................ 471
16.3.1 Port A IO Register (PAIOR) ................................................................................ 479
16.3.2 Port A Control Register (PACR).......................................................................... 479
16.3.3 Port B IO Register (PBIOR) ................................................................................ 484
16.3.4 Port B Control Register (PBCR) .......................................................................... 484
16.3.5 Port C IO Register (PCIOR) ................................................................................ 488
16.3.6 Port C Control Registers 1 and 2 (PCCR1, PCCR2)............................................ 488
16.3.7 Port D IO Register (PDIOR) ................................................................................ 494
16.3.8 Port D Control Register (PDCR).......................................................................... 494
16.3.9 Port E IO Register (PEIOR)................................................................................. 500
16.3.10 Port E Control Register (PECR) .......................................................................... 500
16.3.11 Port F IO Register (PFIOR) ................................................................................. 504
................................................................... 459
................................................................... 473
Rev. 5.00 Jan 06, 2006 page xv of xx