HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 402

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Serial Communication Interface (SCI)
Bit 1:
CKE1
0
0
1
1
Notes: 1. The SCK pin is multiplexed with other functions. Use the pin function controller (PFC) to
13.2.7
The serial status register (SSR) is an 8-bit register containing multiprocessor bit values, and status
flags that indicate SCI operating status.
The CPU can always read and write the SSR, but cannot write 1 in the status flags (TDRE, RDRF,
ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after
being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. The SSR is
initialized to H'84 by a power-on reset, in hardware standby mode and software standby mode.
Manual reset does not initialize SSR.
Note:
Rev. 5.00 Jan 06, 2006 page 380 of 818
REJ09B0273-0500
Initial value:
2. Initial value.
3. The output clock frequency is the same as the bit rate.
4. The input clock frequency is 16 times the bit rate.
* The only value that can be written is a 0 to clear the flag.
Serial Status Register (SSR)
Bit 0:
CKE0
0
1
0
1
select the SCK function for this pin, as well as the I/O direction.
R/W:
Bit:
Description *
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
Asynchronous mode
Clock synchronous mode
R/(W) *
TDRE
7
1
R/(W) *
RDRF
1
6
0
R/(W) *
ORER
5
0
Internal clock, SCK pin used for input pin (input
Internal clock, SCK pin used for synchronous
clock output *
Internal clock, SCK pin used for clock output *
Internal clock, SCK pin used for synchronous
clock output
External clock, SCK pin used for clock input *
External clock, SCK pin used for synchronous
clock input
External clock, SCK pin used for clock input *
External clock, SCK pin used for synchronous
clock input
signal is ignored) or output pin (output level is
undefined) *
R/(W) *
FER
4
0
R/(W) *
2
PER
2
3
0
TEND
R
2
1
MPB
R
1
0
MPBT
R/W
0
0
4
4
3