HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 45

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.1.3
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC). The multiply
and accumulate registers store the results of multiply and accumulate operations. The procedure
register stores the return address from the subroutine procedure. The program counter stores
program addresses to control the flow of the processing. Figure 2.3 shows a system register.
2.1.4
Table 2.1 lists the values of the registers after reset.
Table 2.1
Classification
General registers
Control registers
System registers
31
31
31
System Registers
Initial Values of Registers
Initial Values of Registers
Register
R0–R14
R15 (SP)
SR
GBR
VBR
MACH, MACL, PR
PC
Figure 2.3 System Register Configuration
MACH
MACL
PR
PC
Initial Value
Undefined
Value of the stack pointer in the vector address table
Bits I3–I0 are 1111 (H'F), reserved bits are 0, and other
bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector address
table
0
0
0
Multiply and accumulate (MAC)
registers high and low (MACH,
MACL): Stores the results of
multiply and accumulate operations.
Procedure register (PR): Stores
a return address from a
subroutine procedure.
Program counter (PC): Indicates
the fourth byte (second instruction)
after the current instruction.
Rev. 5.00 Jan 06, 2006 page 23 of 818
REJ09B0273-0500
Section 2 CPU